An LQFP-240 package is almost always a 240-lead quad flat pack on a 32 × 32 mm body at 0.5 mm pitch, and almost never a true 1.4 mm low-profile part. Distributors and CAD libraries use “LQFP-240” as a catalog string; the silicon vendors ship it as QFP240, PQ240, or PRQP0240. That gap changes your height budget, your thermal margin, and occasionally your enclosure. Here are the numbers that matter.
Key Takeaways
- The parts that actually ship at 240 leads are QFPs on a 32 × 32 mm body, 2.45 mm to 3.4 mm thick. Not 1.4 mm.
- Amkor’s LQFP line runs 7 × 7 mm to 28 × 28 mm at 32 to 256 leads under JEDEC MS-026. There is no 240-lead entry, and the lead-pitch arithmetic explains why.
- Budget 3.4 mm of Z-height until the specific vendor drawing says otherwise. A 2 mm assumption error is a respin.
- 240 leads buy I/O, not cooling. Xilinx measured 19.4 °C/W still-air θJA on PQ240 against 13.2 °C/W on the heatsink-bearing HQ240.
- Nearly every 240-lead device is legacy silicon. AMD closed last-time-buy on Spartan-II and Spartan-3 on 29 June 2024, which moves counterfeit screening from optional to mandatory.
What “LQFP-240” Actually Refers To
LQFP-240 is a 240-lead plastic quad flat package with gull-wing leads on all four sides, 60 leads per side, 0.5 mm lead pitch, and a 32 × 32 mm body. Bodies ship between 2.45 mm and 3.4 mm thick, so most parts sold under the name are QFP, not low-profile LQFP.
The naming gap is not pedantry. Amkor, which assembles the family, defines LQFP as a 1.4 mm body across 7 × 7 mm to 28 × 28 mm sizes and 32 to 256 leads, every variation built to JEDEC MS-026. Xilinx labels its 240-lead part PQ240 and describes the outline as EIAJ 32 × 32 at 0.5 mm pitch. NXP registers the same footprint as SOT1701-1, drawing 98ASH70075A, at 32 × 32 × 3.4 mm. Mouser files 240-lead FPGAs under PQFP-240. Nobody who manufactures the package calls it LQFP-240.
The string survives because parametric search fields and library generators flatten every gull-wing quad package into “LQFP-nn”. Search the term and you get sockets, PGA adapters, and 3D models cut to the 240-pin outline. Search a datasheet and you get QFP.
[IMAGE 1: Top and side view of a 240-lead 32 × 32 mm quad flat package with pin 1 corner dot, 60 leads per side, 0.5 mm pitch callout | alt: “LQFP-240 package outline showing 32 × 32 mm body, 0.5 mm pitch and 60 leads per side”]
LQFP-240 Dimensions: What Actually Ships
Four 240-lead outlines account for most of what an engineer will encounter. They share a land pattern. They do not share a height.
| Designation | Body (mm) | Thickness | Pitch / leads per side | θJA still air, typ | Reference document |
| QFP240 (SOT1701-1) | 32 × 32 | 3.4 mm | 0.5 mm / 60 | not published | NXP drawing 98ASH70075A, ref F-PQFP-G240 |
| PQ240 / PQG240 | 32 × 32 | 3.4 mm | 0.5 mm / 60 | 19.4 / 24.9 °C/W | Xilinx UG112 v2.0, listed as EIAJ 32 × 32 |
| HQ240 / HQG240 | 32 × 32 | 3.4 mm | 0.5 mm / 60 | 13.2 / 12.9 °C/W | Xilinx UG112 v2.0, heat spreader board-side |
| PRQP0240KC-A | 32 × 32 | 2.45 mm | 0.5 mm / 60 | not published | Renesas SH7200-series 240-pin QFP |
The thickness column is the one that causes trouble. Renesas ships a 2.45 mm body on the same 32 × 32 mm footprint that Xilinx and NXP fill at 3.4 mm. Both are drop-in on the PCB and neither is drop-in under a 3 mm lid. Mass diverges just as hard: the HQ240 weighs 15.0 g against 7.1 g for PQ240, more than double the load on the same 240 solder joints, which changes how the assembly behaves under shock and board flex.
Why a True 1.4 mm LQFP-240 Does Not Exist
Run the geometry. Sixty leads per side at 0.5 mm pitch puts 59 pitches, or 29.5 mm, between the outermost lead centers. Amkor’s largest MS-026 body is 28 × 28 mm with a 30.0 mm tip-to-tip lead span. The leads do not fit.
| Body size | Lead counts offered (MS-026) | Tip-to-tip span | Room for 240 leads at 0.5 mm? |
| 14 × 14 mm | 64 / 80 / 100 / 120 / 128 | 16.0 mm | No |
| 20 × 20 mm | 128 / 144 / 176 | 22.0 mm | No |
| 24 × 24 mm | 160 / 176 / 216 | 26.0 mm | No, and 240 is not a listed count |
| 28 × 28 mm | 208 / 256 | 30.0 mm | No: 60 leads need 29.5 mm of centers |
| 32 × 32 mm | Not an MS-026 LQFP body | n/a | This is where 240 leads live, as QFP |
Dropping to 0.4 mm pitch would compress 60 leads into 23.6 mm, which suits a 24 × 24 mm body. That body exists in the MS-026 family at 160, 176, and 216 leads. It is not offered at 240. The 240-lead count falls into the gap between two registered configurations, which is exactly why it lives in the thicker EIAJ-derived QFP outline instead of the low-profile one.
The practical consequence: if a library part or a BOM line reads LQFP-240 and quotes 1.4 mm, the height is wrong. Pull the vendor drawing before mechanical sign-off, not after.
LQFP-240 Pinout: Numbering, Orientation, and What Not to Assume
Two hundred forty leads divide into four sides of 60. Pin 1 occupies a corner, marked by a molded dot or chamfer, and numbering runs counterclockwise viewed from the top, meaning the marked face. Xilinx states this convention for its PQFP parts in UG112. The ceramic CQFP family reverses it and runs clockwise from the top, which is a real trap if you inherit a footprint from a ceramic design.
Side boundaries land at pins 60/61, 120/121, and 180/181. Corner pins on a 240-lead device are frequently tied to ground or left as no-connect, because corner leads carry the longest bond wires and the worst lead inductance in the package.
No common pinout exists for the outline. A Spartan-XL XCS40XL-5PQ240C and an MC68360 QUICC share the mechanical package and nothing electrical. Treat “LQFP-240 pinout” as a per-device question and pull the specific datasheet.
[IMAGE 2: Pin numbering diagram for a 240-lead QFP showing pin 1 corner marker, counterclockwise sequence, and side boundaries at 60, 120, 180 | alt: “LQFP-240 pinout diagram with 60 pins per side numbered counterclockwise from the pin 1 corner”]
Footprint and Land Pattern for a 240-Lead, 0.5 mm Pitch QFP
Land pattern geometry follows IPC-7351B. For gull-wing leads at pitch below 0.625 mm, the standard applies the same toe and heel fillet goals as coarser pitches and tightens only the side goal. Working from Amkor’s verified 0.60 mm foot length and IPC Density Level B fillet targets gives the following.
| Parameter | Value | Basis |
| Lead foot length | 0.60 mm | Amkor LQFP datasheet DS232G |
| Lead standoff | 0.10 mm | Amkor LQFP datasheet DS232G |
| Toe fillet goal, Jt | 0.35 mm | IPC-7351B Density Level B |
| Heel fillet goal, Jh | 0.35 mm | IPC-7351B Density Level B |
| Side fillet goal, Js | 0.03 mm | IPC-7351B Density Level B |
| Fabrication + placement allowance | 0.10 mm each | IPC-7351B standard assumption |
| Resulting pad length | ≈ 1.45 mm | Foot + toe + heel + allowance |
| Practical pad width | 0.24 – 0.28 mm | Industry practice at 0.5 mm pitch |
| Copper gap between pads | ≈ 0.22 mm | 0.5 mm pitch minus pad width |
| Minimum solder-mask web | 0.10 mm | Typical fabricator limit |
Two numbers deserve attention. The 0.22 mm copper gap between adjacent pads sits barely above a 0.10 mm minimum solder-mask web, so mask-defined separation between every pair of the 240 pads is marginal by construction. And 60 pads per side means only the outermost one or two rows escape on the surface layer; everything else needs a via, so plan the fan-out and layer count before you commit to the package.
For stencil design, 0.10 mm to 0.12 mm foil with 1:1 apertures is the usual starting point, with a modest area reduction along the pad’s long axis if bridging appears at first article. Lead coplanarity, not paste volume, is what produces most open joints on a body this large.
Thermal Budget: 240 Leads Are Not a Heat Sink
Xilinx published a worked case in UG112 that maps directly onto this package. An XCV400E in PQ240 has a still-air θJA of 17.9 °C/W. At 2.70 W dissipation and 55 °C ambient, junction temperature reaches 55 + (17.9 × 2.70) = 103.3 °C, which misses a 100 °C design target. Add 250 LFM of forced air and θJA falls to 13.2 °C/W, giving 55 + (13.2 × 2.70) = 90.6 °C. Roughly 2.5 W is the still-air ceiling for a bare 240-lead QFP against a 100 °C junction limit.
The heatsink-bearing variant changes the arithmetic. HQ240 measures 13.2 °C/W typical still-air θJA and 1.5 °C/W θJC against 3.8 °C/W for PQ240. One detail bites: at 240 pins and below, Xilinx mounted the heat spreader on the board side of the package to preserve pin compatibility with PQ, so the low θJC path runs into the PCB, not out the top. Clamping an external sink to the lid will not deliver the datasheet number. Pour copper and add thermal vias instead.
Lead-free variants pay a measurable penalty. PQG240 shows 24.9 °C/W typical still-air θJA against 19.4 °C/W for the leaded PQ240, a difference large enough to move a marginal design across the line.
Lead Parasitics: Where 240 Pins Stop Helping
Amkor’s 100 MHz simulation of the 208-lead, 28 × 28 mm LQFP is the nearest characterized neighbor and sets expectations. Longest lead: 9.67 nH inductance, 1.38 pF capacitance, 86.2 mΩ resistance. Shortest lead: 6.19 nH, 1.21 pF, 64.8 mΩ. A 32 mm body with 60 leads per side extends the corner leads further, so corner parasitics get worse, not better.
Ten nanohenries of loop inductance on a fast edge is why 240-lead devices dedicate so many pins to ground and why simultaneous switching output limits on these parts are conservative. If you need high-speed switching on more than a handful of pins, the package is your ceiling, not the die. That is the point at which a BGA stops being optional.
Assembly, MSL, and the Failure Modes That Actually Appear
Amkor qualifies the LQFP family at JEDEC moisture sensitivity level 3, characterized at 30 °C/60% RH for 192 hours, with temperature cycling from −65 °C to +150 °C for 500 cycles, unbiased HAST at 130 °C/85% RH for 96 hours, 1000 hours of high-temperature storage at 150 °C, and AEC-Q100 qualification available. MSL 3 on a body this large is not a formality. Popcorning risk scales with molded volume, and 32 × 32 mm is near the top of what still gets built on a leadframe.
Lead-free handling is more forgiving here than on array packages. Leadframe parts plate matte tin and tolerate either process: J-STD-020 peak reflow of 245 °C to 260 °C for Pb-free, or 205 °C to 220 °C for SnPb. BGA solder balls do not melt properly at the lower profile. That backward compatibility is one reason the 240-lead QFP persists in repair and legacy production.
Four failure modes account for most returns on this package. Bent leads from handling, and these parts get handled often at 24 devices per tray. Coplanarity drift producing opens along one side. Bridging at the 0.22 mm copper gap. And pad cratering under the heavier heatsink variant when the board flexes during depanel or connector insertion.
[IMAGE 3: Cross-section of a leadframe QFP showing die attach pad, gull-wing lead form, standoff, and foot length dimensions | alt: “Cross-section of a 240-lead QFP showing gull-wing lead form, 0.10 mm standoff and 0.60 mm foot length”]
Sourcing, Lifecycle, and Counterfeit Exposure
Most 240-lead quad flat devices are mature or obsolete. AMD closed last-time-buy on Spartan-II, Spartan-3, XC9500, and CoolRunner on 29 June 2024. NXP’s SOT1701-1 package page lists MC68360 QUICC variants, a family older than many of the boards still carrying it. Renesas SH7200-series 240-pin parts sit in the same lifecycle band.
That produces three procurement behaviors worth writing into a build standard. Buy from franchised stock, or from a distributor that publishes test-and-trace results. Budget for X-ray or decapsulation on any brokered lot, because the counterfeit population targeting legacy programmable logic in 240-pin QFP is well established. And verify RoHS status by date code rather than by base part number, since leaded and lead-free versions share an outline and frequently share a shelf.
Which 240-Lead Package Should You Specify?
Work the decision in this order. If Z-height under 2.5 mm is a hard constraint, only the thinner 2.45 mm QFP body qualifies, and only if the device you need is offered in it; otherwise the answer is BGA. If dissipation exceeds roughly 2.5 W in still air, specify the heatsink variant or commit to forced air at design time rather than discovering the shortfall at thermal validation.
If this is a new design at any I/O count, do not start here. A 240-lead QFP consumes 1024 mm² of board area to deliver on the order of 190 usable I/O, with corner-lead inductance near 10 nH. A comparable BGA does the same work in a quarter of the area with better parasitics and a lower assembly defect rate.
If the board must be hand-reworkable, field-repairable, or is a retrofit into an existing layout, the 240-lead QFP remains the correct answer. Visible, probeable, reflowable leads are the whole reason it survives.
Frequently Asked Questions
Is LQFP-240 the same as QFP-240?
In practice they refer to the same 240-lead, 32 × 32 mm, 0.5 mm pitch outline and share a land pattern. Formally they are not equivalent: LQFP denotes a 1.4 mm body under JEDEC MS-026, and no 240-lead MS-026 variation exists. Treat “LQFP-240” on a listing as shorthand for QFP-240.
What are the dimensions of an LQFP-240 package?
Body is 32 × 32 mm with 0.5 mm lead pitch and 60 leads per side. Thickness depends on vendor: NXP’s SOT1701-1 and Xilinx’s PQ240 are 3.4 mm, while Renesas’s 240-pin QFP measures 2.45 mm. Gull-wing leads extend past the body on all four sides.
How many pins are on each side of a 240-pin QFP?
Sixty per side. Pin 1 sits in a marked corner and numbering advances counterclockwise viewed from the top of the package, so side boundaries fall at pins 60/61, 120/121, and 180/181. Ceramic CQFP packages reverse this and number clockwise from the top.
What land pattern should I use for a 240-lead 0.5 mm pitch QFP?
Start at roughly 0.25 mm × 1.45 mm pads on 0.5 mm centers, derived from a 0.60 mm foot length plus IPC-7351B Density Level B fillet goals of 0.35 mm at toe and heel. That leaves about 0.22 mm of copper gap, so confirm your fabricator can hold a 0.10 mm solder-mask web.
Can you hand-solder a 240-pin QFP?
Yes. Gull-wing leads at 0.5 mm pitch are drag-solderable with flux, a chisel tip, and braid for cleanup, which is why the package persists in repair work. Alignment is the hard part: tack two opposite corners first, verify all four sides against the pads, then run the remaining edges.
What to Do Next
If you are keeping an existing board alive, specify the exact vendor outline rather than the generic name, confirm the body thickness against the drawing, and route your purchasing through franchised stock with date-code-level RoHS verification. If you are laying out a new footprint, build it from the vendor drawing at IPC Density Level B and check the solder-mask web with your fabricator before releasing.
If you are choosing a package for a design that has not been committed yet, the 240-lead QFP earns its place only when hand rework, field repair, or a legacy footprint constrains you. On board area, thermal headroom, and lead parasitics, a BGA wins on every axis that a 240-lead quad flat pack competes on.
Internal Links (proposed)
- [INTERNAL LINK: 240-pin PQFP FPGA families → legacy Xilinx package guide]
- [INTERNAL LINK: BGA vs QFP for high pin count → package selection comparison]
- [INTERNAL LINK: IPC-7351B land pattern density levels → PCB footprint design guide]
- [INTERNAL LINK: moisture sensitivity level and floor life → SMT assembly handling guide]
- [INTERNAL LINK: counterfeit component screening → obsolete part sourcing guide]
External References
- Amkor LQFP Data Sheet DS232G: https://amkormarcomexternal.blob.core.windows.net/amkordotcom/wp-content/uploads/2018/02/LQFP_DS232.pdf
- NXP package SOT1701-1 (QFP240): https://www.nxp.com/packages/SOT1701-1
- Xilinx Device Package User Guide UG112 v2.0: https://wwwpub.zih.tu-dresden.de/~ss17/wiki/www.es.inf.tu-dresden.de/forschung/spartanmc/docs/xilinx/ug112.pdf
- JEDEC MS-026-D registration: https://www.jedec.org/standards-documents/docs/ms-026-d
- IPC-7351B standard: https://shop.ipc.org/ipc-7351/ipc-7351-standard-only/Revision-b/english
