A QFP exposed pad only works if it is soldered. Solder it properly and the same die runs roughly 44% cooler than in a standard package on the same board, per Texas Instruments SLMA002H. Leave it dry and the datasheet thermal numbers do not apply, because they were measured with the pad attached. The design work is four decisions: land size, via array, paste volume, and electrical net.

[IMAGE 1: Cross-section of a QFP with exposed pad soldered to a thermal land, showing the 0.1 mm standoff between the lead seating plane and the pad landing plane, plus thermal vias into an inner plane | alt: “QFP exposed pad soldered to a PCB thermal land with thermal vias”]

Key Takeaways

• On a QFP the exposed pad sits about 0.1 mm above the lead seating plane, with a tolerance of ±0.05 mm (Infineon, Recommendations for Board Assembly of Infineon Quad Flat Packages, rev. 6.0). A QFN has no such gap. That single dimension changes every paste and land rule you copy across.
• Print more paste on a QFP exposed pad than you would on a QFN. Infineon recommends roughly 70% to 80% pad coverage, explicitly less reduction than a leadless package needs.
• TI caps the copper land for TQFP PowerPAD parts at package body size minus 2.0 mm, then defines the solderable area with solder mask sized to the datasheet maximum exposed pad.
• Target at least 50% post-reflow solder joint area over the pad (TI SLMA002H). Ordinary unoptimised assembly usually delivers over 80%.
• TI and Infineon disagree on solder mask defined versus non-solder-mask defined lands. Follow the vendor whose part you are placing, and do not mix definitions in one footprint.
• Too much paste is a failure mode, not a safety margin. Excess solder under the pad lifts the body off its perimeter leads and turns a thermal design problem into an open-joint problem.

What the QFP Exposed Pad Actually Buys You

A QFP exposed pad is the underside of the leadframe die paddle, left uncovered by mold compound so it can be soldered to a copper land on the board. It gives heat a short metal path from die to PCB instead of forcing it out through the gull-wing leads, and on most parts it also grounds the die paddle.

The gain is large and measurable. TI reports that a PowerPAD device soldered to its recommended board runs about 44% cooler than the same standard package on that same board, and about 73% cooler than a standard package on a JEDEC low-conductivity board.

Translated into power budget, TI lists a 20-pin SSOP at 0.75 W in the standard version and 3.25 W with the pad, and a 24-pin TSSOP at 0.55 W against 2.32 W, both assuming a 150 °C junction and 80 °C ambient. The ratio for QFP bodies is the same order.

One caveat governs every number you read off a datasheet. As Analog Devices states in its exposed pad design note, the quoted θJC assumes the exposed pad is soldered or thermally bonded to the board unless the datasheet says otherwise. An unsoldered pad does not degrade the specification gracefully; it invalidates it.

The 0.1 mm Standoff That Separates QFP From QFN

Search results for exposed pad layout are dominated by QFN guidance, and most of it transfers badly. The reason is geometric.

On a QFN, the perimeter lands and the thermal pad lie in one plane. On a QFP, the gull-wing feet form the seating plane and the exposed pad sits above it. Infineon defines that gap as the package standoff and puts it at a nominal 100 µm, varying by ±50 µm. JEDEC allows 0.05 mm to 0.15 mm standoff for TQFP and TSSOP bodies, which is the same window from the other direction.

So the solder under a QFP exposed pad has to bridge a real gap, while QFN solder only has to fill a joint line. Three consequences follow.

• Paste volume must be higher. Infineon states the recommended print reduction for QFP die pads is smaller than for leadless packages precisely because of the standoff.
• Underprinting does not merely reduce thermal performance, it can leave the pad unwetted entirely, at which point θJA reverts to the leads-only value.
• Overprinting floats the body. TI records this directly in its rework guidance: if too much solder forms on the die pad, the component sits above the perimeter leads and causes coplanarity problems.

That last point is worth restating because it is where most of these designs actually fail. The pad and the leads compete for the same vertical budget, and the pad wins.

Sizing the Thermal Land

Two published rules bound the land, and they come at it from opposite ends.

TI gives an upper limit: for TQFP packages the maximum copper land size is the package body size minus 2.0 mm. A solder mask defined pad is then placed on that copper, sized to the maximum exposed pad dimension in the device datasheet. The copper outside the mask opening still spreads heat.

Infineon gives a lower limit: the exposed pad area on the PCB should be congruent with the package area at minimum, and matching the package pad size also improves solder joint reliability. Infineon adds a detail nobody else publishes. Some QFP exposed pads carry an anti-flash profile, a meander structure around the pad outline that catches mold flash during fabrication. Use the outer extension including that profile as the reference for the PCB pad, not the plain rectangle.

On pad definition the two vendors part company. TI recommends solder mask defined lands to prevent shorting between the exposed pad and the package leads. Infineon recommends NSMD for QFP, applied to both the peripheral terminations and the exposed pad, and warns against mixing definitions in one footprint. Neither is wrong; they are optimising different things, TI for short prevention on a mask-controlled geometry, Infineon for joint reliability on a copper-controlled geometry. Follow the vendor whose part is in the socket.

Keep clearance between the pad land and the lead lands. NXP specifies at least 0.25 mm between the outer edge of the thermal land and the inner edge of the lead pattern.

Thermal Vias: Diameter, Pitch, and Solder Wicking

Vias carry heat out of the land into inner planes. Published guidance converges more than the pad rules do.

Parameter	TI (SLMA002H)	NXP (AN4388)	Infineon (QFP rev. 6.0)	Toshiba (SOP/QFP guide)
Via drill diameter	0.33 mm or smaller	0.30 to 0.33 mm	0.2 to 0.5 mm typical	0.30 to 0.33 mm
Via array pitch	1.5 mm (TI test board)	1.2 mm grid	1.0 to 1.2 mm starting point	Set from package perimeter
Via barrel plating	1 oz copper	1 oz copper	Fill or overplate small vias	About 20 µm copper
Via count guidance	5 to 9 for small die	Application specific	Diminishing returns; analyse	Perimeter placement preferred
Paste coverage on pad	Aperture per foil thickness	50% to 80% of pad area	About 70% to 80% of pad area	Solder area at least 50%
Stencil thickness	0.10 to 0.178 mm	0.13 to 0.20 mm by pitch	0.13 to 0.15 mm at 0.5 mm pitch	0.125 to 0.175 mm
Post-reflow joint area	At least 50%; over 80% typical	80% to 90% of pad area	Judge by X-ray voiding	At least 50% of E-Pad

Table 1. Exposed-pad QFP layout parameters as published by four vendors

Two rules matter more than the numbers.

First, no thermal relief. TI is explicit that vias in the thermal land must connect to the plane with a continuous connection completely around the hole diameter, and that wagon-wheel spoke construction is not acceptable here. Thermal relief exists to make hand soldering easier; on this land it defeats the purpose of the via.

Second, keep solder out of the barrel. An open via wicks paste away from the joint, thins the standoff, and can push solder through to the far side of the board. The published options, in order of cost:

• Position the vias where there is no paste. Infineon suggests placing vias under the beam intersections of a segmented stencil pattern, which lets you run open vias on both sides and still form a sound joint.
• Cap with solder mask on the component side, sized to the via diameter plus at least 0.1 mm (TI). Tenting from the opposite side instead measurably increases voiding, because flux outgassing and trapped air have nowhere to go.
• Plug with epoxy and overplate. Infineon notes vias 100 µm in diameter or smaller should be copper-filled and overplated, and that the fill must be specified planar so no cavity is left to form voids.
• Add a wettable dummy area around the vias on the far side to catch surplus solder and prevent beading, if you keep the vias open.

Adding vias has diminishing returns. TI found five to nine vias adequate for a small die and shows the board thermal resistance curve flattening beyond that. Infineon puts it plainly: a constant increase in via count does not translate into a constant decrease in assembly thermal resistance.

Stencil Design for the Exposed Pad

This is the step that decides whether the design works. TI publishes a stencil aperture table for the 64-pin, 14 × 14 × 1.0 mm TQFP PowerPAD package that shows the logic clearly: as the foil gets thicker, the centre aperture shrinks.

Foil thickness	Centre aperture (square)	Printed paste volume
0.100 mm	5.55 mm	3.08 mm³
0.127 mm	5.19 mm	3.42 mm³
0.152 mm	4.90 mm	3.65 mm³
0.178 mm	4.60 mm	3.77 mm³

Table 2. TI centre-pad stencil openings for the 64-pin TQFP PowerPAD package, with printed volume computed from the published dimensions

Volume is held within about 20% across a 78% change in foil thickness. That is the whole idea: the aperture is not a fixed fraction of the land, it is whatever delivers the right volume for the standoff you have to fill. Aperture ratios follow from volume, not the other way round.

Two mechanical constraints shape the pattern. Apertures larger than roughly 5 mm are prone to squeegee scooping, so segment them into a windowpane. NXP recommends the segments be spaced at least 0.15 mm apart and the overall exposed-pad aperture be 0.25 mm smaller than the copper pad for registration.

Worked Example: 64-Pin TQFP With Exposed Pad

Take the TI 64-pin PAP body at 0.127 mm foil, printing a 5.19 mm square centre aperture. Assume a 5.5 mm square exposed pad; use your own datasheet value.

• Printed paste volume: 5.19² × 0.127 = 3.42 mm³.
• Solder paste is roughly 50% metal by volume, which is TI’s stated modelling assumption and matches Infineon’s figure of about 50% flux and additives by volume. Solder volume after reflow is therefore near 1.7 mm³.
• Spread over a 5.5 mm square pad, 30.3 mm², that is a mean joint thickness of about 0.056 mm.
• Compare against the standoff you must fill: 0.05 mm to 0.15 mm per JEDEC, or 0.10 mm ±0.05 mm per Infineon. The joint lands at the bottom of that window with nothing to spare.

Now apply a QFN habit and cut the print to 50% coverage. Solder volume falls to roughly 1.0 mm³ and mean thickness to about 0.033 mm, below the minimum standoff. The pad may not wet at all, and you will not see it, because the joint is under the body. This is the single most common way such a design silently loses its thermal budget.

The correction runs the other way for a QFN, where the standoff is near zero and the same volume floats the part. Copying either direction blindly produces a defect.

[IMAGE 2: Windowpane stencil aperture over a QFP exposed pad, with thermal vias positioned under the beam intersections so no paste prints over an open barrel | alt: “Windowpane stencil aperture over a QFP exposed pad with vias at the beam intersections”]

Electrical Connection: Ground, Float, or Neither

The pad is a die paddle, not a signal pin, and vendors treat it differently. Analog Devices summarises the field accurately: some pads must be connected to the ground plane, some must be electrically disconnected, and some accommodate both. Blindly grounding a pad that carries a supply node produces a low-impedance short that costs a board spin to find.

For microcontroller-class parts the guidance is more settled. NXP engineering bulletin EB806 notes the exposed pad is not a circuit terminal but forms a plane under the die, and recommends connecting it to MCU ground for EMC. For automotive or safety-critical designs NXP states the pad should be soldered to the PCB and connected to MCU ground.

Practical rule: check the datasheet electrical connections table before you attach the land to a plane, and treat a floating copper pour under a die as a liability rather than a neutral choice.

Failure Modes and Inspection

The joint is invisible, so the defects are found late unless you plan for them.

• Floating and lead opens. Excess pad solder lifts the body off its leads. Symptom is corner-lead opens on a part that looks correctly placed.
• Voiding. Infineon notes large exposed pads tend to void more because the volume-to-surface ratio is poor for outgassing. Extent depends on pad size, via and stencil layout, paste, and profile.
• Solder escape through open vias, thinning the joint and beading on the far side.
• Early solder fatigue from board stiffness. Infineon warns against placing exposed-pad packages directly opposite each other on the two sides of a board; offset them.

Inspection splits cleanly. AOI covers the gull-wing leads, which is the one real advantage this package retains over a QFN. The pad joint needs automated X-ray. TI notes X-ray can be run in monitor mode or at 100% if the application demands it. Broken joints, as Infineon points out, are still not easy to see in X-ray, so process control beats inspection here.

For rework, expect a harder job than the lead pattern suggests. TI publishes worked machine settings for a 100-pin TQFP: removal at 240 °C and 0.10 scfm for a 60 s preheat, then 250 °C at 0.65 scfm for 15 s. The thermal enhancement that helps the device in service also drains heat away from your rework nozzle.

Frequently Asked Questions

Do you have to solder the exposed pad on a QFP?

Yes, if you want the datasheet thermal numbers. TI states plainly that PowerPAD packages are not designed to be used without the exposed pad soldered, citing both thermal performance and mechanical integrity. Analog Devices adds that quoted θJC assumes the pad is soldered or thermally bonded unless the datasheet says otherwise.

How much solder paste should go on a QFP exposed pad?

More than on a QFN. Infineon recommends roughly 70% to 80% coverage of the pad area for QFP, a smaller reduction than leadless packages need, because the QFP pad sits about 0.1 mm above the lead seating plane. Size the aperture from the volume required to fill that standoff, then segment it if it exceeds about 5 mm.

How many thermal vias does an exposed-pad QFP need?

Fewer than most layouts use. TI found five to nine vias adequate for a small die, with the thermal resistance curve flattening beyond that. Typical geometry is 0.3 mm to 0.33 mm drill on a 1.0 mm to 1.5 mm grid with 1 oz barrel plating. Run thermal and electrical analysis rather than filling the land by reflex.

Should the QFP exposed pad be connected to ground?

Usually, but verify first. Some pads must go to ground, some must be electrically isolated, and some allow either, per Analog Devices. NXP recommends grounding the pad on its MCUs for EMC and requires it for automotive and safety-critical designs. Check the datasheet electrical connections table before tying the land to a plane.

Is a QFP with an exposed pad as good as a QFN?

Thermally the QFN usually edges ahead because its pad sits directly on the board. The QFP keeps two advantages: visible, AOI-inspectable lead joints, and a real standoff that absorbs board flex. For prototyping, field rework, or boards that see mechanical stress, those often outweigh a few °C/W.

What to Do Next

Before you release the footprint, pull three numbers: the maximum exposed pad dimension from the package drawing, the standoff range, and the electrical net for the pad. Size the land between the Infineon congruence floor and the TI body-minus-2.0 mm ceiling, then set the stencil aperture from the paste volume that fills your standoff rather than from a coverage percentage borrowed from a QFN note.

On the first build, X-ray the pad joint and measure the void fraction before you tune anything else. If joint area is already over 80%, spend your effort on via construction and plane connection. If it is under 50%, the paste volume is wrong, and no amount of extra vias will recover the thermal budget you never had.

Sources

• Texas Instruments SLMA002H, PowerPAD Thermally Enhanced Package, November 1997, revised July 2018.
• Infineon, Recommendations for Board Assembly of Infineon Quad Flat Packages, revision 6.0, 12 November 2020.
• NXP (Freescale) AN4388, Quad Flat Package (QFP), rev. 2.0, February 2014.
• NXP engineering bulletin EB806, Electrical Connection Recommendations for the Exposed Pad on QFN and DFN Packages, rev. 0.
• Toshiba, Package Mounting Guide SOP/QFP, revision 1.0, 17 March 2016.
• Analog Devices, Exposed Pads: A Brief Introduction.
• Renesas, Thermal Design for Packages (QFP heat spreader and HQFP exposed die pad variants).
• JEDEC JESD51-2, JESD51-5, JESD51-7 and JESD51-8, thermal test board and measurement standards; IPC-7525 and IPC-7351B.