A TSSOP-48 package measures 12.4 mm to 12.6 mm long by 6.0 mm to 6.2 mm wide, with 48 leads on 0.5 mm pitch, a 7.9 mm to 8.3 mm lead span and a 1.2 mm maximum height. Unlike most lead counts in this family, 48 is a registered JEDEC variation, and Texas Instruments, Nexperia and Infineon all publish the same envelope. The footprint is the easy part here; routing it is not.

Key takeaways

• TSSOP-48 dimensions per TI drawing DGG0048A: body 12.4 mm to 12.6 mm by 6.0 mm to 6.2 mm, lead span 7.9 mm to 8.3 mm, pitch 0.5 mm, height 1.2 mm max.
• 48 leads appear in JEDEC’s registered MO-153 list, which is why three vendors agree on the geometry. Lower counts like 32, 38 and 44 do not appear there.
• The land pattern is 48 lands of 1.5 mm by 0.3 mm on 0.5 mm pitch with rows at 7.5 mm, leaving a 0.2 mm gap between adjacent lands.
• Plain TSSOP-48 logic ships at moisture sensitivity Level 1 with unlimited floor life, not the Level 3 rating that exposed-pad HTSSOP parts carry.
• The same 16-bit die is sold in TSSOP-48 and the 300-mil SSOP-48 body: 6.1 mm against 7.5 mm width, 1.2 mm against 2.8 mm height, 89 °C/W against 94 °C/W.

[IMAGE 1: dimensioned top, side and end view of a 48-lead TSSOP with pitch, lead span and height called out | alt: “TSSOP-48 package dimensions showing 0.5 mm pitch and 8.1 mm nominal lead span”]

The least ambiguous package in the TSSOP family

JEDEC Publication 95, in its index by device type, lists MO-153 with registered lead counts of 8, 14, 16, 20, 24, 28, 36, 40, 48, 52, 56, 60, 64 and 68. That 48 is on the list matters. Package names in this family are usually a hint rather than a specification, and 48 leads is one of the few counts where the hint holds.

Three vendors bear that out. TI draws DGG0048A as a 12.5 mm by 6.1 mm nominal body on 0.5 mm pitch. Nexperia describes SOT362-1 as a plastic thin shrink small outline package with 48 leads and a 6.1 mm body width, referencing MO-153. Infineon lists PG-TSSOP-48-2 with a 12.5 mm body length, 6.1 mm body width and 0.5 mm minimum terminal pitch, with no exposed paddle.

TI’s legacy mechanical sheet MTSS003D shows how the body scales inside one drawing: 12.40 mm to 12.60 mm for 48 pins, 13.90 mm to 14.10 mm for 56, and 16.90 mm to 17.10 mm for 64, all on the same 6.0 mm to 6.2 mm width and 7.9 mm to 8.3 mm span. Move up a lead count and only the length changes.

TSSOP-48 dimensions

Table 1 lists the controlled dimensions from TI drawing DGG0048A, revision 4214859/B dated November 2020.

Table 1. TSSOP-48 mechanical data, dimensions in mm

Parameter	Value	Note
Leads	48, 24 per side	46 spaces at 0.5 mm
Lead pitch	0.5	11.5 mm lead row per side
Body length	12.4 to 12.6	excludes mold flash up to 0.15 mm per side
Body width	6.0 to 6.2	the 6.1 mm TSSOP body
Lead span	7.9 to 8.3 typ	across the gull wings
Height	1.0 to 1.2	1.2 mm maximum
Standoff	0.05 to 0.15
Lead width	0.17 to 0.27	against a 0.3 mm land
Foot length	0.50 to 0.75	gage plane at 0.25 mm
Lead angle	0 to 8 degrees
Exposed pad	none on the DGG outline	thermal path is through the leads and board
JEDEC reference	MO-153	48 leads is a registered variation

Nothing here is unusual for the family. What is unusual is the density: 48 connections inside a 12.5 mm by 6.1 mm outline, which is why the routing problem outweighs the mechanical one.

TSSOP-48 footprint and stencil

TI’s example land pattern uses 48 lands of 1.5 mm by 0.3 mm at 0.5 mm pitch, with the two rows dimensioned at 7.5 mm, non solder mask defined, and 0.05 mm of mask clearance all around. The stencil example uses the same 1.5 mm by 0.3 mm apertures on a 0.125 mm foil, with no reduction, because there is no thermal pad to balance.

The number to check with your fabricator is the gap between lands: 0.5 mm pitch minus a 0.3 mm land leaves 0.2 mm of bare laminate. That is comfortable for most shops as a mask dam, but confirm it rather than assume, and keep the lands non solder mask defined so the fillet geometry stays predictable.

Land pattern area comes out at about 106 mm²: 11.8 mm along the rows, from 23 spaces at 0.5 mm plus one land width, by 9.0 mm across, from the 7.5 mm row dimension plus one land length. Budget roughly 12.5 mm by 10 mm of keepout once you allow courtyard.

Escape routing is the real constraint. With a 0.2 mm gap between lands, a single trace between adjacent pads needs the trace plus two clearances to fit inside 0.2 mm, which most fabricators will not quote at standard rates. Plan on breaking out inner pins with vias between the land rows or on the outside, not with traces threaded between pads.

[IMAGE 2: land pattern with 48 lands, row dimension and the 0.2 mm gap between adjacent lands called out | alt: “TSSOP-48 footprint with 1.5 mm by 0.3 mm lands on 0.5 mm pitch”]

TSSOP-48 pinout: the 16-bit logic convention

Numbering follows the usual rule: pin 1 at the index feature, counterclockwise from the top view, pins 1 to 24 down one side and 25 to 48 back up the other. Function assignment belongs to the device, but this lead count is dominated by 16-bit logic, and that family shares a convention worth knowing.

Take the SN74ALVCH162244, a 16-bit buffer. Its A inputs sit on pins 26 to 47 and the Y outputs on pins 2 to 23, so signals flow across the package rather than doubling back. Ground occupies pins 4, 10, 15, 21, 28, 34, 39 and 45, and VCC occupies pins 7, 18, 31 and 42.

Count that up: 12 of 48 pins, a quarter of the package, are power and ground, distributed at roughly every fifth pin. That is deliberate, since 16 outputs switching together need short return paths, and it means your escape plan has a via every few pins for free if you place the supply vias sensibly.

The flow-through arrangement also decides board placement. Put the device so that the A side faces its source and the Y side faces its load, and the 16-bit bus routes without crossing. Rotate it and you will spend layers undoing that.

Thermal reality for a package with no pad

TI publishes 89 °C/W junction-to-ambient for the DGG package and 94 °C/W for the wider DL body, calculated per JESD 51. Neither package has a thermal pad, so heat leaves through 48 leads and the board copper.

Logic parts look harmless until you sum the switching. Dynamic power is approximately the sum of the power dissipation capacitance and the load capacitance, times supply voltage squared, times frequency, times the number of switching outputs.

Work an example with the datasheet values. The SN74ALVCH162244 lists power dissipation capacitance of 19 pF at 3.3 V. Add a 30 pF load, run all 16 outputs at 50 MHz on a 3.3 V rail, and dissipation is about 0.43 W. At 89 °C/W that is a 38 °C junction rise, which puts the die near 123 °C in an 85 °C ambient.

The decision rule follows directly: below roughly 0.3 W the package is comfortable anywhere in its rated range, and above that you either slow the bus, reduce load capacitance, or accept a hotter die. There is no thermal land to improve, so copper under the leads and airflow are the only levers you have.

TSSOP-48 against SSOP-48: same die, two bodies

Most 16-bit logic in this class is sold in both bodies. TI offers the DGG TSSOP and the DL 300-mil SSOP; NXP and Nexperia offer SOT362-1 as TSSOP48 and SOT370-1 as SSOP48. Table 2 sets out what changes.

Table 2. The same 48-lead 16-bit logic die in two package bodies

Attribute	TSSOP-48 (TI DGG, Nexperia SOT362-1)	SSOP-48 (TI DL, Nexperia SOT370-1)
Body width	6.0 to 6.2 mm	7.5 mm
Height	1.2 mm max	2.8 mm max
Junction-to-ambient	89 °C/W	94 °C/W
Tube quantity	40 pieces	25 pieces
Tape width and reel	24 mm tape, 2000 per 330 mm reel	32 mm tape, 1000 per 330 mm reel
Pocket depth K0	1.8 mm	3.1 mm
Moisture sensitivity	Level 1, 260 °C, unlimited floor life	Level 1, 260 °C, unlimited floor life
Chooses itself when	height or width is constrained	hand rework or wider pitch is preferred

The thermal gap is small, 5 °C/W, so the choice is mechanical rather than thermal. The TSSOP saves 1.4 mm of width and 1.6 mm of height and doubles the parts per reel. The SSOP is easier to inspect and rework, and it halves your reel changes only if you were buying tubes anyway.

Sourcing, ordering codes and assembly

Moisture handling is the pleasant surprise. TI rates the SN74ALVCH162244 in DGG at Level 1 with a 260 °C peak and unlimited floor life, per the November 2025 addendum. Compared with the Level 3 and 168 hour floor life common on exposed-pad HTSSOP parts, a TSSOP-48 logic reel can sit open on the line.

One ordering trap is specific to TI. The datasheet notes that for tape and reel entry the DGGR package is abbreviated to GR, so the reel version of SN74ALVCH162244DGG is ordered as SN74ALVCH162244GR. Search a distributor for DGGR and you will find nothing.

Distributor package strings are their own hazard. Digi-Key files the Nexperia 74AVC16T245DGG under 48-TFSOP with a 0.240 inch width in one field and 48-TSSOP in another. Search by pitch and body dimensions instead of the package name.

On price and availability, that Nexperia part listed at 1.63 US dollars in ones and 0.642 dollars in 2000-piece reels, with two pieces in stock and backorders suspended, when checked in August 2026. Cross-vendor second sourcing is realistic here: TI, Nexperia and Infineon build the same outline, and the 16-bit logic pinouts are standardised, so a second source is usually a part-number change rather than a layout change.

Feeder planning is simple. TSSOP-48 ships in 24 mm tape at 12 mm pocket pitch, 2000 per 330 mm reel, with pockets 8.6 mm by 13.0 mm by 1.8 mm deep, or 40 pieces per 530 mm tube for prototypes.

Five mistakes that cost a board spin

1. Planning to route a trace between adjacent lands. The gap is 0.2 mm, so break out with vias instead and confirm your fabricator’s mask dam capability.
2. Placing the device without regard to flow-through pinout, which turns a clean 16-bit bus into a layer-hungry crossover.
3. Treating a logic package as thermally free. Sixteen outputs at 50 MHz into 30 pF is about 0.43 W and a 38 °C rise at 89 °C/W.
4. Ordering DGGR instead of GR from a TI datasheet, or searching a distributor by package name rather than dimensions.
5. Substituting the SSOP-48 body late in the design. It is the same die and pinout but 1.4 mm wider and 1.6 mm taller, which usually breaks the enclosure rather than the schematic.

TSSOP-48 package FAQ

What are the dimensions of a TSSOP-48 package?

Body length is 12.4 mm to 12.6 mm, body width 6.0 mm to 6.2 mm, lead span 7.9 mm to 8.3 mm and height 1.2 mm maximum, on 0.5 mm pitch, per TI drawing DGG0048A. Lead width runs 0.17 mm to 0.27 mm and foot length 0.50 mm to 0.75 mm. Nexperia and Infineon publish the same 12.5 by 6.1 mm envelope.

What is the pitch of a TSSOP-48 package?

It is 0.5 mm, giving 46 spaces and an 11.5 mm lead row on each side. Adapter and stencil vendors list the same 0.5 mm pitch for their 12.5 by 6.1 mm TSSOP-48 hardware. Lower lead counts in the family often use 0.65 mm, so read the pitch from the drawing rather than assuming.

Is TSSOP-48 a JEDEC standard package?

Yes, more so than most. JEDEC’s index by device type lists 48 among the registered MO-153 lead counts, and TI, NXP and Nexperia all reference MO-153 on their 48-lead outlines. That registration is why three manufacturers publish the same body, span and pitch.

What is the difference between TSSOP-48 and SSOP-48?

They are usually the same die in different bodies. TSSOP-48 is 6.1 mm wide and 1.2 mm tall; the 300-mil SSOP-48 is 7.5 mm wide and up to 2.8 mm tall. TI publishes 89 °C/W for the TSSOP and 94 °C/W for the SSOP, so the choice is mechanical rather than thermal.

Can a TSSOP-48 be hand soldered?

Yes, with drag soldering, plenty of flux and braid for cleanup, though 0.5 mm pitch across 24 leads per side is unforgiving. There is no exposed pad to reach, which makes it easier than an HTSSOP. Adapter boards and stencils for 12.5 by 6.1 mm TSSOP-48 are available for prototypes.

What to do next

Pull the drawing for your exact orderable part number, confirm 0.5 mm pitch and a 7.9 mm to 8.3 mm lead span, then lay the footprint as 48 lands of 1.5 mm by 0.3 mm with rows at 7.5 mm, non solder mask defined. That geometry is the same across TI, Nexperia and Infineon, which is rare enough in this family to be worth using.

Spend the design effort on placement and escape instead. Orient the part so the input side faces its source, use the eight ground and four supply pins as your via anchors, and check the switching estimate before assuming a logic package runs cool.

Switch bodies only for mechanical reasons. If height above 1.2 mm is unavailable or width is tight, stay in TSSOP-48. If the board has room and the build is hand-assembled or repeatedly reworked, the 300-mil SSOP-48 version of the same device costs you 1.4 mm of width and buys back inspection access.

[IMAGE 3: side-by-side outlines of TSSOP-48 and the 300-mil SSOP-48 at the same scale | alt: “TSSOP-48 compared with the wider SSOP-48 body at the same scale”]

Internal links

• [INTERNAL LINK: TSSOP-44 package -> TSSOP-44 dimensions, pinout and footprint]
• [INTERNAL LINK: TSSOP-38 package -> TSSOP-38 dimensions, pinout and footprint]
• [INTERNAL LINK: TSSOP-32 package -> TSSOP-32 dimensions, pinout and footprint]
• [INTERNAL LINK: fine-pitch escape routing -> breaking out 0.5 mm pitch packages]
• [INTERNAL LINK: moisture sensitivity level -> MSL floor life, baking and dry pack handling]

External references

• TI SN74ALVCH162244 datasheet, containing drawing DGG0048A and MTSS003D: https://www.ti.com/lit/ds/symlink/sn74alvch162244.pdf
• TI SN74AUC16244 datasheet, same DGG0048A drawing: https://www.ti.com/lit/ds/symlink/sn74auc16244.pdf
• JEDEC Publication 95 index by device type: https://www.jedec.org/sites/default/files/MOIND_DT.pdf
• Nexperia package page SOT362-1 (TSSOP48): https://www.nexperia.com/packages/SOT362-1.html
• NXP 74LVC16244A datasheet, ordering table for TSSOP48 and SSOP48: https://media.digikey.com/pdf/Data%20Sheets/NXP%20PDFs/74LVC(H)16244A_Rev13.pdf