Post: Fudan Micro FPGA: Series, Xilinx Equivalents, Price and Supply

Fudan Micro FPGA is the programmable-logic line from Shanghai Fudan Microelectronics Group (FMSH, 688385.SH and 1385.HK), and in practice you will meet exactly two families on a BOM: the JFM7 series, built on the land patterns of Xilinx Kintex-7 and Virtex-7 devices, and the FMQL / JFMQL PSoC series, built on Zynq-7000 footprints. These parts are not in the Digi-Key catalog. Pricing is quote-only, the toolchain is Procise rather than Vivado, and since September 2025 the parent company sits on the U.S. Entity List. Below is the part list, an honest Xilinx equivalence map, what the devices actually cost, and the board-level rules that decide whether your first article boots.

Key takeaways

• Two families matter commercially: JFM7 (Kintex-7 and Virtex-7 class, FCBGA-900) and FMQL / JFMQL PSoC (Zynq-7000 class, Arm PS plus PL on one die).
• Pin-compatible is real. Software-compatible is not. The FMQL45T900 PS is a quad-core Arm Cortex-A7; the Zynq XC7Z045 it replaces is a dual-core Cortex-A9.
• Expect four figures in RMB per unit. A 2021 public procurement record bought 400 industrial-grade JFM7K325T in FCBGA-900 at RMB 2,960 each.
• There is no open-market stock. Catalog exchanges return zero supply records. The real channels are an authorized mainland agent, direct FMSH sales, or a SoM vendor.
• BIS added Shanghai Fudan Microelectronics to the Entity List on 16 September 2025 with a footnote 4 designation. Clear compliance before you commit a layout.

What Is a Fudan Micro FPGA and Who Actually Makes It

A Fudan Micro FPGA is an SRAM-based programmable logic device designed by Shanghai Fudan Microelectronics Group, an IC design house founded in July 1998 out of Fudan University’s State Key Laboratory of ASIC and Systems. The company listed in Hong Kong in 2000, moved to the HK Main Board in 2014, and added a STAR Market listing in 2021.

The FPGA program is not a side project. In 2023 the FPGA and related product line became the company’s largest revenue segment at roughly RMB 1.139 billion, up 44.8% year on year and about 32% of total revenue. The line ran an 84.7% gross margin in 2022. Remember that number. It explains the pricing section further down better than any market analysis will.

FMSH groups its programmable devices into four families, in the same language its annual reports use:

• Ten-million-gate class. 65 nm, launched 2016. Small logic, long-life industrial sockets.
• Hundred-million-gate class. 28 nm, first shipped in China in Q2 2018, in volume from 2019. This is where JFM7K325T, JFM7K410T and JFM7VX690T live.
• Billion-gate class. 1xnm FinFET, small-batch trial production and customer evaluation from 2023. Not something you design in today unless you are already engaged with FMSH.
• PSoC. Embedded programmable devices that put an Arm processing system and programmable logic on one die. The FMQL and JFMQL parts. There is also an FPAI reconfigurable AI part and an RFSoC.

By the end of 2021 FMSH had sold 28 nm FPGA products to more than 300 customers across communications, industrial control and high-reliability applications. The devices compile in Procise, FMSH’s own full-flow EDA tool, which covers the entire programmable line. Procise is not Vivado, it does not read a Vivado project, and it does not produce a Vivado bitstream.

Fudan Micro FPGA List: JFM7, FMQL and PSoC Part Numbers

This is the list most people are actually searching for. Every device below is a 28 nm part unless noted, and every Xilinx column entry is a footprint and resource target, not a claim of equivalence at any other layer.

Part number	Class	Xilinx target	Package / pitch	Headline resources
JFM7K325T	FPGA, 100M-gate	XC7K325T (Kintex-7)	FCBGA-900, 31 x 31 mm, 1.0 mm	326,080 LUTs, 16 GTX transceivers
JFM7K410T	FPGA, 100M-gate	XC7K410T (Kintex-7)	FCBGA-900, 1.0 mm	Larger logic array than K325T, 16 GTX
JFM7VX690T / JFM7VX690T36	FPGA, 100M-gate	XC7VX690T (Virtex-7)	FCBGA, 900-class, 1.0 mm	Top of the JFM7 logic and transceiver range
FMQL45T900 / JFMQL45T900	PSoC	XC7Z045 (Zynq-7000)	FCBGA-900 (FFG900 footprint), 1.0 mm	Quad-core Arm PS; PL: 350K logic cells, 19.2 Mb BRAM, 900 DSP, 16 GTX
FMQL20S400 / JFMQL20S400	PSoC	Zynq-7000 CLG400 footprint	FCBGA-400, 17 x 17 mm, 0.8 mm	Quad-core Arm PS to 1 GHz; PL: ~28K logic cells, 2.1 Mb BRAM, 80 DSP
JFMQL100TAI900	PSoC with AI engine	No direct Xilinx twin	FCBGA, 900-class, 1.0 mm	PSoC fabric plus AI acceleration
JFM9RFVU3P5G	RFSoC	RFSoC class	Quote-specific	8 RX and 8 TX direct-RF sampling channels

How to Read a Fudan Micro Part Number

• JFM7 prefix: 7-series-class FPGA fabric, no hard processor. The J generally marks the screened, high-reliability line.
• FMQL or JFMQL prefix: PSoC. An Arm processing system and programmable logic on a single die.
• Trailing numbers are ambiguous. The 900 in FMQL45T900 lines up with both 900 DSP slices and a 900-ball package. Do not use it as a shortcut for either. Read the ordering guide.
• Grade, speed and screening level live in the suffix, and they move the price by multiples. Two lines that look identical in a BOM can be a 4x cost difference.

The same die frequently ships in commercial, industrial and high-reliability grades with different screening, different temperature ranges and wildly different prices. Ordering by family name is how a program discovers, at kickoff plus twelve weeks, that it quoted the wrong part.

Fudan Micro FPGA vs Xilinx: Where Pin-Compatible Stops Being Compatible

Pin-compatible is a PCB claim. It says the balls land where your old land pattern expects them. It says nothing about the seven other layers of your project, and those are where schedules die.

Layer	Compatible?	What it means for your schedule
BGA land pattern	Yes	JFM7K325T drops onto the XC7K325T FFG900 pattern. No respin needed for the footprint alone.
Power rails and sequencing	Verify	Rail names line up, but current per rail and ramp requirements do not automatically. Re-derive the PDN from the Fudan datasheet.
Bitstream	No	A Vivado .bit will not configure a JFM7 or FMQL device. The JTAG IDCODE is different and Vivado will not even see the chain.
Toolchain	No	You rebuild in Procise. Budget for constraint translation and a fresh timing closure, not a recompile.
Soft IP	Partial at best	Xilinx MIG, XDMA and the AXI infrastructure IP do not port. You re-source equivalents from the FMSH IP library.
PS software (PSoC parts)	No	FMQL45T900 PS is a quad-core Cortex-A7 at 800 MHz to 1 GHz. The XC7Z045 PS is a dual-core Cortex-A9. Different microarchitecture, different boot chain, different device tree, different BSP.
Package construction	Not identical	The Fudan 400-ball part is a flip-chip BGA. The Zynq CLG400 it replaces is a wire-bond chip-scale BGA. Same footprint, different warpage through reflow.
Speed grade and timing	Verify	Speed grades are benchmarked against imported grades, not guaranteed identical. Re-run timing. Slack does not carry over.

Two things in that table catch teams out, and both are counterintuitive enough to be worth spelling out.

The first is that the layout engineer finishes in an afternoon and the software team loses a quarter. On a Zynq-to-FMQL migration the footprint is the cheapest thing to match. The processing system moved from a dual-core Cortex-A9 to a quad-core Cortex-A7, which means your first-stage bootloader, your device tree, your BSP and any NEON-tuned inner loop all get rewritten. Nobody plans for this, because “pin-compatible” reads like “drop-in” and the hardware evidence keeps agreeing with them right up until the board refuses to boot.

The second is that the same footprint does not mean the same reflow profile. The Fudan FCBGA-400 is a flip-chip package sitting on the identical 0.8 mm, 17 x 17 mm land pattern as the wire-bond Xilinx CLG400. Flip-chip and wire-bond substrates warp differently through the liquidus window. Reuse your old Zynq recipe and the corner balls are where you find out: head-in-pillow on the outer two rows, invisible to AOI, obvious under X-ray, and typically discovered after 200 boards.

How to Buy Fudan Micro FPGA: Distributors, Lead Times and MOQ

Here is the truth: you cannot add one of these devices to a cart. Search JFM7K325T on the Chinese component exchanges and you get zero supply records. Search it on the Western catalog distributors and you get nothing at all. The brand pages that currently rank for “fudan micro distributor” are broker landing pages carrying FMSH EEPROM and RFID parts, with no FPGA line item behind them.

Three channels actually work:

• Authorized mainland agent, project-registered. Quote-only. This is how most volume programs buy.
• Direct through FMSH sales, for programs with real volume or a high-reliability requirement.
• SoM and evaluation-board vendors who already carry the device. You buy the module, not the chip. Fastest way to get silicon on a bench.

If you are going through the chip channel, run it in this order:

1. Freeze the ordering part number. A family name is not a part number. Grade, speed, package and screening level all sit in the suffix and all move the price.
2. Run compliance before layout, not after. See the export-control section below. This is the step teams skip and then pay for.
3. Register the project with the agent. Domestic FPGA channels price by project, not by catalog. An unregistered RFQ gets you a placeholder number that will not survive contract.
4. Ask for the ordering guide and the errata in writing. Not the marketing brief. If an agent will not send an errata sheet, that is your answer about the agent.
5. Buy a qualification lot before you buy production. Twenty to fifty pieces, one date code, full traceability from tray label to invoice.
6. Plan 8 to 16 weeks and buffer it. Industrial and high-reliability 28 nm parts are not shelf stock, and the screened grades are the ones that slip.

Because there is no open-market catalog stock, any broker who claims stock deserves a hard look. Ask for the date code, the lot number and a photograph of the tray label before you send money. On receipt, X-ray a sample from every lot and read the JTAG IDCODE before you trust the marking. A re-marked Kintex-7 will sail through visual inspection and fail on IDCODE in about four seconds.

Fudan Micro FPGA Price: What Engineers Actually Pay

The honest answer is that a Fudan Micro FPGA usually costs more than the Xilinx part it replaces, not less.

One concrete, dated reference point: a 2021 public procurement record out of Xi’an lists 400 pieces of industrial-grade JFM7K325T in FCBGA-900 at RMB 2,960 per unit, RMB 1,184,000 for the lot. Call it roughly USD 410 a device at the rate of the day. Pricing has moved since, and grade dominates the number more than volume does.

Device class	Grade	Indicative unit price	What drives it
PSoC, 400-ball (FMQL20S400 class)	Industrial	Low four-figure RMB	Cheapest entry into the family. Smallest PL.
FPGA, 900-ball (JFM7K325T class)	Industrial	Around RMB 3,000 (2021 tender: RMB 2,960)	The reference point most programs anchor on.
FPGA, 900-ball (JFM7VX690T class)	Industrial	A multiple of the K325T	Logic array and transceiver count.
Any of the above	High-reliability / screened	2x to 5x the industrial price	Screening and traceability, not different silicon.

Domestic substitution is a supply-security decision, not a cost-reduction decision. If your business case depends on the Chinese part being cheaper, the business case is wrong.

The 84.7% gross margin on the FPGA line is the whole story. Companies running 84% margins are not competing on unit price. They are selling supply continuity, localization compliance and a domestic support line with engineers who answer the phone in your timezone. If that is what your program needs, it is worth paying for. If you simply want a cheaper Kintex-7, buy a Kintex-7.

The trade-off is real and it goes both ways. You give up BOM cost, toolchain maturity, IP ecosystem depth and the enormous body of public reference designs that comes with Vivado. You get a supply chain that does not depend on an export licence and a part that satisfies a domestic-content requirement. Programs that need the second thing pay for the first four without complaining. Programs that do not need it should not be here.

Export Control and Compliance: What Changed in September 2025

Not one of the pages currently ranking for this keyword mentions this, which tells you something about the pages currently ranking for this keyword.

On 16 September 2025 the U.S. Bureau of Industry and Security added Shanghai Fudan Microelectronics and affiliated entities, including the Beijing, Shenzhen and Hong Kong entities, to the Entity List. The addition carries a licence requirement for all items subject to the EAR and a licence review policy of presumption of denial. Shanghai Fudan Microelectronics also received a footnote 4 designation, which extends the licence requirement to foreign-produced items under the Foreign Direct Product Rule. BIS cited support for China’s military modernization and the supply of technology to Russian military end users. A follow-on BIS rule dated 29 September 2025 extends Entity List restrictions automatically to entities that are 50% or more owned by a listed party. The rule text is public: Additions and Revisions to the Entity List, Federal Register, 16 September 2025.

What that does and does not mean, in plain terms:

• The Entity List governs what you export to the listed company. It is not, by itself, a ban on importing their chips.
• It does restrict supplying them U.S.-origin items, technology and software. That includes design data, technical collaboration, and U.S.-origin test and programming equipment.
• It changes the risk picture for anyone with a U.S. nexus, U.S. government customers, or a compliance function that reads the Entity List before breakfast.

That is a factual summary and not legal advice. Export-control lists change, and the exact legal entity names on the list matter more than the brand name on the chip. Get a written position from your trade-compliance counsel before you commit a design, not after your first article ships.

PCB Design and SMT Assembly Rules for Fudan Micro FPGA BGA Packages

The devices come in two package families you will actually build: FCBGA-900 (900 balls, 31 x 31 mm body, 1.0 mm ball pitch) for the JFM7 and FMQL45 parts, and FCBGA-400 (400 balls, 17 x 17 mm body, 0.8 mm pitch) for the smaller PSoC. Everything below follows from those two numbers.

Stack-Up, Escape Routing and Controlled Impedance

A 900-ball BGA does not automatically need HDI, and a lot of teams overspend here out of reflex. At 1.0 mm pitch you can dog-bone escape with a 0.25 mm drill and a 0.5 mm pad, routing one 0.10 mm trace between adjacent vias on a standard subtractive process. A 12 to 16 layer through-hole board handles the FCBGA-900 without a single microvia. HDI and via-in-pad start earning their cost at 0.8 mm pitch and below, which is exactly where the FCBGA-400 lives.

Specify controlled impedance properly: 50 ohm single-ended and 100 ohm differential, +/-10% as standard, +/-5% if the GTX lanes are running anywhere near their ceiling. Ask the fab for a stack-up proposal and a coupon impedance report, not a verbal assurance that they will hit it.

The transceivers are where laminate choice stops being a preference and starts being a budget. GTX lanes on the FFG900-class footprint reach 12.5 Gb/s, which puts the Nyquist fundamental at 6.25 GHz. Standard FR-4 runs a dissipation factor around Df 0.020 at 10 GHz. A low-loss laminate such as Panasonic Megtron 6 or Rogers RO4350B sits near Df 0.004, roughly five times lower. In practice a 10-inch stripline that burns 6 to 9 dB on FR-4 lands closer to 2 to 3 dB on the low-Df stack, before you have spent anything on connectors and vias. Run the channel budget. Do not eyeball it.

And back-drill the transceiver vias. On a 16-layer board a through-hole via serving a top-layer GTX lane leaves a stub over 1 mm long. At 6.25 GHz that stub is a resonator sitting in your signal path, and it will close the eye far more effectively than any laminate choice will open it.

Reflow, Inspection and IPC Acceptance

Handle these as moisture-sensitive devices and check the MSL rating on the tray label before the tray leaves the dry cabinet. If floor life is blown, bake per J-STD-033 before reflow. Nobody has ever regretted a bake. Plenty of people have regretted running a popcorned flip-chip.

Build the reflow profile for this package, not for the package it replaced. That point is worth repeating because it is the single most common failure on a Xilinx-to-Fudan swap. Start with a 0.12 mm stencil and 1:1 apertures on a 1.0 mm pitch BGA, verify paste volume with SPI, and profile with thermocouples under the package body rather than trusting an oven recipe inherited from a different substrate.

X-ray every FPGA, not a sample. On a 900-ball flip-chip, the joints you cannot see are precisely the joints that fail, and the device costs more than the inspection by two orders of magnitude. This is standard practice in competent BGA assembly and it should be a line item in your quote, not an afterthought.

Read the X-ray against IPC-7095, not against a single number. IPC-A-610 calls a Class 2 defect when the cumulative projected void area within a ball exceeds 25%. But IPC-7095 is explicit that void location matters more than void area: a 24% void sitting in the centre of a ball can be perfectly serviceable, while a 12% void at the pad interface is the one that cracks under thermal cycling. If you need Class 3, agree the acceptance criteria in writing with your assembler before the first build, because both standards allow the OEM and the assembler to set their own limits.

For end use in industrial, rail, energy or defence, fabricate to IPC-6012 Class 3 and assemble to IPC-A-610 Class 3 with J-STD-001 workmanship. Class 2 is fine for a lab bring-up. It is not fine for a fifteen-year field life, and a competent PCB assembly partner will tell you which one you actually need rather than quoting whichever is cheaper.

A Case That Cost Six Weeks and No Hardware

An anonymized example from a power-monitoring customer. They moved a Zynq XC7Z045 design to an FMQL45T900 on the same FFG900 footprint. Layout took two days. The first twenty boards came off the line, passed AOI, passed X-ray with a worst-case void of 11%, and three of them would not boot the processing system. The solder was fine. Every joint was fine. The boot image was not: the quad-core Cortex-A7 PS needs a different first-stage bootloader and a different device tree than the dual-core Cortex-A9 they had been shipping for four years. The fix cost six weeks of software time and not a single board. Every hardware signal in that project said the migration was clean, and every hardware signal was telling the truth.

Common Fudan Micro FPGA Sourcing and Design Mistakes

Send this list to whoever is doing the migration.

1. Treating pin-compatible as drop-in. It is a land-pattern claim and nothing more.
2. Quoting by family name. JFM7K325T is not a part number until it carries a grade, speed and screening suffix.
3. Assuming Vivado will talk to the chip. It will not. Install Procise and absorb the learning curve before you commit the schedule, not after.
4. Copy-pasting the Xilinx power delivery network. Re-derive current per rail and the sequencing window from the Fudan datasheet.
5. Reusing the Zynq reflow recipe on the flip-chip part. Different substrate, different warpage, corner-ball head-in-pillow.
6. Sampling X-ray on a 900-ball FPGA. Inspect all of them. The part costs more than the inspection.
7. Reading void percentage without void location. IPC-7095 is clear that where the void sits matters more than how big it is.
8. Skipping the errata. Every 28 nm FPGA has one. If the agent will not send it, escalate until someone does.
9. Buying broker “stock” with no tray-label photo. There is no open-market stock for these parts, so anything that looks like stock deserves a JTAG IDCODE check on arrival.
10. Designing it in before compliance clears it. Since September 2025 that is a career-limiting mistake at a lot of primes.

Three things worth doing on Monday

• Pull the ordering guide and errata for your exact part number and diff the power table line by line against your existing Xilinx PDN.
• Send your stack-up to the fab and ask what impedance tolerance they can actually hold on the GTX pairs, +/-10% or +/-5%, and what it costs to move from one to the other.
• Get a written position from trade compliance on the current Entity List status before you spend another hour on layout.

Frequently Asked Questions About Fudan Micro FPGA

Is the Fudan Micro FPGA a Xilinx clone?

It is a domestically designed device benchmarked against a specific Xilinx part and built to the same land pattern. JFM7K325T targets the XC7K325T, FMQL45T900 targets the XC7Z045. The die, the bitstream format and the toolchain are FMSH’s own. Treat it as a same-footprint replacement, not a copy.

Can I use Vivado with a Fudan Micro FPGA?

No. Fudan Micro devices compile in Procise, FMSH’s own full-flow EDA tool, which supports the entire programmable-device line. A Vivado bitstream will not configure a JFM7 or FMQL part, and Vivado will not recognise the JTAG IDCODE on the chain. Plan a full rebuild and a fresh timing closure.

Where can I buy Fudan Micro FPGA chips?

Not from a catalog. The Western distributors and the Chinese component exchanges both return zero supply records for JFM7K325T. The working routes are an authorized mainland agent with your project registered, direct FMSH sales for volume programs, or a SoM vendor who already carries the device on a module.

How much does a Fudan Micro FPGA cost?

Expect four figures in RMB per unit. A 2021 public procurement record priced 400 industrial-grade JFM7K325T in FCBGA-900 at RMB 2,960 each. High-reliability screened grades run two to five times that. Pricing is quote-only and project-registered, so a number off a broker page is not a real number.

Is Fudan Microelectronics on the US Entity List?

Yes. BIS added Shanghai Fudan Microelectronics and affiliated entities on 16 September 2025, with a licence requirement for all items subject to the EAR, a presumption of denial, and a footnote 4 designation extending the rule to foreign-produced items. Confirm the current entry with your trade-compliance counsel.

Is FMQL45T900 a drop-in replacement for the Zynq XC7Z045?

For the PCB, yes. It uses the same FFG900 land pattern. For the software, no. The FMQL processing system is a quad-core Arm Cortex-A7 running at 800 MHz to 1 GHz, against the XC7Z045’s dual-core Cortex-A9. Bootloader, device tree and BSP all get rewritten.

What temperature range do Fudan Micro FPGAs support?

Industrial-grade devices and the boards built around them are commonly specified at -40 C to +85 C operating, with storage extending to -55 C. High-reliability grades go further. Confirm the range against the ordering suffix on your exact part number rather than the family datasheet.

Building a Fudan Micro FPGA Board Without the Surprises

The Fudan Micro FPGA is a serious device with a serious catch. The footprint is the easy part. Everything stacked above it, the bitstream, the toolchain, the PS software, the reflow window and the compliance file, is where programs actually slip. Get the ordering part number right including the grade suffix. Get the errata in writing. Treat the package as a new package rather than the one it replaces, and X-ray every device that goes down.

Send us your Gerber, stack-up and BOM and we will come back with a DFM review and a quote on the build.