HTSSOP-38 is not one package. Two incompatible outlines ship under that name: a 9.7 mm × 4.4 mm body on 0.5 mm pitch, and a 12.5 mm × 6.1 mm body on 0.65 mm pitch. Their lead spans differ by 1.7 mm and their exposed pads differ by a factor of 2.7 in area. Order an HTSSOP-38 land pattern from a library without checking which one you have and the footprint will not fit.

Key takeaways

• Two outlines, one name. TI ships DCP0038A (9.7 × 4.4 mm, 0.5 mm pitch) and DAP0038E (12.5 × 6.1 mm, 0.65 mm pitch). Both are referenced to JEDEC MO-153 and both are sold as 38-HTSSOP.
• The physically larger outline has the smaller thermal pad. DAP0038E tops out at 2.54 mm × 1.96 mm against 4.70 mm × 2.90 mm on DCP0038A.
• That shows up in the data. Junction-to-case (bottom) is 0.9 °C/W on a DCP part and 2 °C/W on a DAP part.
• Renesas gives the 0.5 mm pitch version a JEDEC variation letter: MO-153 BDT-1. Use it when you talk to a fab or a librarian.
• Size the solder mask opening to the exposed pad on the specific datasheet. Draw the copper larger if creepage allows.
• The two outlines also ship on different tape. 16 mm for the 0.5 mm pitch part, 24 mm for the 0.65 mm pitch part, which is a feeder change on the line.

Two HTSSOP-38 outlines, and how to tell them apart

HTSSOP is a vendor name for a thin shrink small outline package with an exposed die-attach pad underneath. Texas Instruments brands its version PowerPAD. Renesas uses the HTSSOP name directly. Analog Devices and NXP call the same construction TSSOP with an exposed pad. At 38 leads, that name covers two different bodies.

An HTSSOP-38 is a 38-lead thin shrink small outline package with an exposed thermal pad on its underside, built in two variants: a 9.7 mm × 4.4 mm body on 0.5 mm pitch with a 6.4 mm lead span, and a 12.5 mm × 6.1 mm body on 0.65 mm pitch with an 8.1 mm lead span. Maximum seated height is 1.2 mm for both.

The quickest field test is pitch. Nineteen leads per side at 0.5 mm gives a 9.0 mm lead-to-lead span across the row. At 0.65 mm it gives 11.7 mm. If the part measures roughly 12.5 mm end to end, you have the wide one.

Table 1. The two HTSSOP-38 outlines compared

Parameter	TI DCP0038A (4218816/A, 10-2018)	TI DAP0038E (4223749/A, 05-2017)
Body length	9.6 to 9.8 mm	12.4 to 12.6 mm
Body width	4.3 to 4.5 mm	6.0 to 6.2 mm
Lead pitch	0.5 mm	0.65 mm
Lead span	6.2 to 6.6 mm	7.9 to 8.3 mm
Lead width	0.17 to 0.27 mm	0.19 to 0.30 mm
Seated height	1.2 mm max	1.2 mm max
Standoff	0.05 to 0.15 mm	0.05 to 0.15 mm
Exposed pad (max)	4.70 × 2.90 mm	2.54 × 1.96 mm
Exposed pad area (max)	13.6 mm²	4.98 mm²
Carrier tape width	16 mm	24 mm

Both drawings cite JEDEC registration MO-153. Neither one gives a variation letter, which is where a third source earns its keep: Renesas states that its 38-lead HTSSOP is compliant with MO-153 variation BDT-1. That designation applies to the 0.5 mm pitch, 4.4 mm body version.

[IMAGE 1: side-by-side bottom views of the two HTSSOP-38 outlines with body, pitch and exposed pad dimensions labeled | alt: “HTSSOP-38 package bottom views comparing the 0.5 mm and 0.65 mm pitch outlines and their thermal pad sizes”]

Exposed pad size across four vendor drawings

Even inside the 0.5 mm pitch family, the pad is not standardized. Three suppliers publish three different geometries for the same body.

Table 2. Exposed pad and mask opening on four HTSSOP-38 / TSSOP-38-EP drawings

Drawing	Exposed pad	Mask opening	Area	Pitch
TI DCP0038A	3.94 to 4.70 × 2.43 to 2.90 mm	4.70 × 2.90 mm	13.6 mm²	0.5 mm
Renesas M38.173C (Rev 0, 4-2010)	4.60 ± 0.10 × 3.20 ± 0.10 mm	4.60 × 3.20 mm land	14.7 mm²	0.5 mm
Analog Devices FE38 variation AA (Rev C, 09-2010)	4.75 × 2.74 mm ref	4.75 × 2.74 mm min metal	13.0 mm²	0.5 mm
TI DAP0038E	1.94 to 2.54 × 1.36 to 1.96 mm	2.54 × 1.94 mm	4.98 mm²	0.65 mm

The spread inside the 0.5 mm pitch group is about 13 percent by area, which a solder-mask-defined pad absorbs without complaint. The gap to DAP0038E is not in that category. A footprint drawn for one will not solder the other.

Analog Devices labels its 4.75 mm × 2.74 mm figure as the recommended minimum PCB metal size for exposed pad attachment, not as a maximum. TI publishes its number as the maximum exposed pad and expects the mask opening to match it. Read the note on the drawing before you copy the number.

Drawing the HTSSOP-38 land pattern

TI publishes a worked example board layout on each package drawing. For DCP0038A: 38 lead lands of 1.50 mm × 0.30 mm on 0.5 mm pitch, 5.80 mm between the centres of the two rows, a thermal copper area of 9.7 mm × 3.4 mm under the body, and a solder mask opening of 4.70 mm × 2.90 mm inside it.

For DAP0038E: 38 lead lands of 1.50 mm × 0.45 mm on 0.65 mm pitch, 7.50 mm between row centres, 9 mm × 4 mm of thermal copper, and a 2.54 mm × 1.94 mm mask opening. Both drawings note that the metal size may change to satisfy creepage.

Two geometries, not one. Copper can and should be larger than the pad, because copper area is what carries heat sideways into the board. The mask opening defines what actually solders. TI allows 0.05 mm of mask registration all around in its examples.

Lead land length is a design choice, and vendors disagree. TI draws 1.50 mm lands. Analog Devices recommends 1.05 mm × 0.315 mm for the same body. The shorter land buys routing room between the package and neighbouring parts. The longer one gives a bigger visible fillet and easier rework. IPC-7351 density levels cover the same trade, so pick one deliberately rather than inheriting it from whichever library loaded first.

Use a solder-mask-defined thermal land with non-solder-mask-defined lead lands. At 0.5 mm pitch the gap between the pad edge and the inner tip of a lead land is small, and a mask web there is what stops the pad joint bridging out to a signal.

[IMAGE 2: HTSSOP-38 land pattern showing the solder mask defined thermal land, NSMD lead lands and the 1.2 mm via grid | alt: “HTSSOP-38 land pattern with solder mask defined thermal land, 0.3 mm lead lands and 0.2 mm thermal vias on a 1.2 mm grid”]

Thermal vias under the HTSSOP-38 exposed pad

Both TI drawings show 0.2 mm finished vias on a 1.2 mm grid. On DCP0038A that grid spans three pitches along the pad length, so eight vias fit comfortably inside the mask opening. On DAP0038E the 2.54 mm × 1.94 mm opening leaves room for only a handful, which is the second reason that outline runs hotter.

TI application report SLMA002 supplies the limits behind those numbers. A drill of 0.33 mm or smaller works with 1 oz plated copper without wicking excessive solder off the joint. Five to nine vias are adequate for a small die, and the published curves flatten quickly past that. Thermal relief spokes are not allowed under the pad, so connect each barrel to the plane with a full annulus.

If the vias are not plugged during plating, cap them with solder mask on the component side using an opening at least equal to the via diameter plus 0.1 mm. Tenting from the far side instead produces measurably more voiding on x-ray, because flux volatiles and trapped air have nowhere to go. Both TI drawings restate the short version: vias under paste should be filled, plugged or tented.

HTSSOP-38 stencil apertures and paste coverage

TI prints aperture dimensions per stencil thickness on the HTSSOP-38 package drawings themselves. Each drawing assumes a single rectangular aperture over the thermal land and shrinks it as the foil gets thicker, because paste volume rather than footprint area is what the aperture controls.

Table 3. TI thermal-land stencil apertures for both 38-pin PowerPAD TSSOP outlines

Stencil thickness	DCP0038A aperture	DAP0038E aperture
0.100 mm	5.25 × 3.24 mm	2.84 × 2.17 mm
0.125 mm	4.70 × 2.90 mm	2.54 × 1.94 mm
0.150 mm	4.29 × 2.65 mm	2.32 × 1.77 mm
0.175 mm	3.97 × 2.45 mm	2.15 × 1.64 mm

At 0.125 mm the aperture equals the mask opening exactly, a 1:1 ratio. That is the reference case, and both tables are built around it.

Whether to keep the single aperture is a process call. TI recommends a minimum solder joint area of 50 percent of the package thermal pad and reports that ordinary board assembly reaches better than 80 percent with no tuning. JEDEC standoff for TSSOP is 0.05 mm to 0.15 mm, and that is the window a correct paste volume has to land in.

Many assemblers segment the aperture into a windowpane anyway to vent flux. IPC-7093 Section 6.1.5.3 treats small voids in the thermal pad region as unlikely to degrade thermal or electrical performance, and the limit the standard sets is 50 percent void area by cross section. Power and automotive designs commonly hold tighter internally. On the DAP outline, where the pad is under 5 mm², splitting a 2.54 mm × 1.94 mm aperture is rarely worth the web width you lose.

[IMAGE 3: single versus windowpane stencil apertures over an HTSSOP-38 thermal land | alt: “HTSSOP-38 stencil design comparing a single 1:1 aperture with a segmented windowpane pattern on the thermal pad”]

What the pad difference costs you

Two shipping parts make the comparison concrete. The DRV8711 stepper pre-driver uses DCP0038A. The TLC6C5724-Q1 automotive LED driver uses DAP0038E. Both sets of numbers come from TI simulations on JEDEC boards.

Table 4. Thermal metrics for the two HTSSOP-38 outlines, from shipping devices

Metric	DRV8711, DCP (38)	TLC6C5724-Q1, DAP (38)	Unit
RθJA junction-to-ambient	32.7	39.6	°C/W
RθJC(top) junction-to-case top	17.2	31.2	°C/W
RθJB junction-to-board	14.3	18	°C/W
ψJT junction-to-top parameter	0.5	0.8	°C/W
ψJB junction-to-board parameter	14.1	18.1	°C/W
RθJC(bot) junction-to-case bottom	0.9	2	°C/W
Exposed pad area (max)	13.6	4.98	mm²

Junction-to-case (bottom) is the metric that isolates the pad, and it tracks roughly inversely with pad area across these two drawings. These are different dies in different devices, so treat that as a direction rather than a formula. The direction is unambiguous: the bigger package is the worse heat path.

Put it in budget terms. With a 150 °C maximum junction temperature and a 125 °C ambient, the DAP outline allows 25 °C / 39.6 °C/W = 0.63 W. The DCP outline allows 25 °C / 32.7 °C/W = 0.76 W. Same pin count, same nominal package family, 21 percent more headroom.

Worked example: 24 LED channels at 125 °C ambient

The TLC6C5724-Q1 sinks up to 50 mA per channel across 24 channels, with a minimum output voltage of 0.67 V at 50 mA and VCC = 3.6 V. Take 1 V of output headroom as a realistic operating point.

Output dissipation is 24 × 50 mA × 1 V = 1.20 W. Supply current at 50 mA per channel with an 8 MHz grayscale clock is 13.5 mA typical, so VCC adds about 5 V × 13.5 mA = 0.07 W. Package dissipation is roughly 1.27 W with every channel on.

At the 125 °C ambient the device is rated for, 39.6 °C/W puts the junction near 175 °C. That is above the 150 °C absolute maximum and past the 150 °C to 170 °C thermal error threshold. The part will trip.

To stay inside 150 °C you need about 0.63 W, which is roughly half of what all channels at full current draw. In practice that means a PWM duty cycle near 50 percent, half the per-channel current, or a lower ambient. Working from board temperature instead, a 105 °C board with the 18.1 °C/W junction-to-board parameter gives about 128 °C, which is already inside the 125 °C to 145 °C pre-thermal warning band.

None of that is a defect in the device. It is what a 4.98 mm² thermal pad does at automotive ambient, and it is the calculation to run before the layout is frozen.

Failure modes worth designing against

Four of the five common HTSSOP-38 assembly escapes are decided at layout, not on the line.

• Wrong outline entirely. A DCP footprint under a DAP part misses the lead lands by 0.15 mm per pitch and grows to a 1.7 mm span error at the ends. Check pitch and body length before you place the part.
• Mask opening drawn to the copper. On DCP0038A that means opening 9.7 mm × 3.4 mm instead of 4.70 mm × 2.90 mm, and the pad joint then reaches the inner tips of the lead lands.
• The part floats and tilts. A full-area paste print on the thermal land melts before the lead joints and lifts the package. At 0.5 mm pitch the perimeter joints have very little margin to give.
• Solder drains into open vias. Standoff drops below the 0.05 mm JEDEC minimum, the pad joint thins, and solder balls appear under the body. Plug, fill or tent from the component side.
• Feeder mismatch at build. The 0.5 mm pitch part ships on 16 mm tape, the 0.65 mm pitch part on 24 mm tape. Both are 330 mm reels at 12 mm pitch, so the reel looks familiar and the feeder is not.

Sourcing, taxonomy and lifecycle

Distributor taxonomy hides the distinction that matters. Digi-Key files a 38-pin HTSSOP under a Package / Case value of 38-TFSOP (0.173 inch, 4.40 mm width) Exposed Pad, and carries 38-HTSSOP only as the supplier device package string. A plain TSSOP-38 gets the identical Package / Case string minus the words Exposed Pad. Those two words are the entire difference between a part that needs a thermal land and one that does not.

Handling classes differ between the two outlines as well. TI ships the DRV8711 in DCP at moisture sensitivity level 2 with a one-year floor life and a 260 °C peak reflow classification. The TLC6C5724-Q1 in DAP is MSL 3 at 260 °C with a 168 hour floor life. If your line runs a single dry-storage rule for HTSSOP, that assumption is wrong for one of them.

Lifecycle is mixed. TI lists the tube-packed DRV8711DCP as LIFEBUY with the tape-and-reel DRV8711DCPR still active, per the package addendum dated 23 March 2024. STMicroelectronics has its 38-HTSSOP CLT01-38S4 protection array on last-time-buy at Digi-Key with a 1 February 2026 cutoff, listed at $1.76 per unit in the 1,250-piece tube. NXP is still shipping into the outline: the PCA9956BTWY LED driver showed 1,936 units in stock at $3.50 in single quantity and $1.60 at 2,500, checked 11 August 2026.

For second sourcing inside the 0.5 mm pitch family, the mechanical case is good. TI, Renesas and Analog Devices all publish the same body, the same lead span and pads within 13 percent of each other by area, so a mask opening sized to the largest of them lands correctly on all three.

Frequently asked questions

What are the HTSSOP-38 package dimensions?

It depends on which outline you have. The 0.5 mm pitch version has a 9.6 mm to 9.8 mm body length, 4.3 mm to 4.5 mm width and a 6.2 mm to 6.6 mm lead span. The 0.65 mm pitch version measures 12.4 mm to 12.6 mm by 6.0 mm to 6.2 mm with a 7.9 mm to 8.3 mm span. Both are 1.2 mm maximum height.

What size is the HTSSOP-38 thermal pad?

There is no single value. TI DCP0038A is 4.70 mm × 2.90 mm at maximum, Renesas M38.173C is 4.60 mm × 3.20 mm nominal, Analog Devices FE38 variation AA is 4.75 mm × 2.74 mm reference, and TI DAP0038E is only 2.54 mm × 1.96 mm. Take the number from the datasheet for the exact orderable part.

Is HTSSOP-38 the same as TSSOP-38?

The lead outline is the same and both trace to JEDEC MO-153. HTSSOP adds an exposed die-attach pad on the underside, which changes the land pattern, the stencil and the thermal numbers. A board laid out for a plain TSSOP-38 has no thermal land, so an HTSSOP-38 dropped into it loses its main heat path.

Do I have to solder the HTSSOP-38 thermal pad?

Yes, on every device that specifies one. NXP states for its HTSSOP38 parts that the exposed pad must be soldered to a corresponding thermal pad on the board, with thermal vias for heat conduction, and that the pad is tied to supply ground internally. TI takes the same position for PowerPAD, citing mechanical integrity as well as heat.

How many thermal vias does an HTSSOP-38 need?

Five to nine covers a small die according to TI SLMA002, with returns flattening past that. TI example patterns place 0.2 mm vias on a 1.2 mm grid, which yields around eight inside the DCP0038A mask opening. The DAP0038E opening is small enough that via count stops being the limiting factor.

What JEDEC variation is the HTSSOP-38?

The TI drawings cite MO-153 without a variation letter. Renesas is more specific and states that its 38-lead HTSSOP, the 9.70 mm × 4.4 mm body on 0.50 mm pitch, is compliant with MO-153 variation BDT-1. Quote that when you need a fabricator or a library maintainer to agree on which outline you mean.

What to do next

Start by identifying the outline, not the package name. Read the pitch and the body length off the mechanical drawing in the datasheet for your exact orderable part number, and note the drawing number in the corner. Then size the mask opening to the exposed pad on that sheet, draw the copper as large as creepage allows, and place 0.2 mm to 0.3 mm vias on a 1.2 mm grid, plugged or tented from the component side and tied to a plane with full annular rings.

If the part dissipates under roughly 0.5 W, a 0.125 mm stencil with a single 1:1 aperture is fine and you can skip x-ray. Above that, or in anything automotive, segment the aperture, agree a void limit before the first build, and inspect. And if you are landing on DAP0038E for a part that dissipates real power, run the junction temperature calculation first, because a 4.98 mm² pad at 125 °C ambient will not carry much more than 0.6 W.

Sources

Texas Instruments, DRV8711 datasheet (SLVSC40H), containing the DCP0038A package outline drawing and thermal metrics. https://download.mikroe.com/documents/datasheets/DRV8711_datasheet.pdf

Texas Instruments, TLC6C5724-Q1 datasheet (SLASEK2A), containing the DAP0038E package outline drawing and thermal metrics. https://www.ti.com/lit/ds/symlink/tlc6c5724-q1.pdf

Texas Instruments, DAP0038E package outline drawing 4223749/A. https://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/196/4223749_5F00_Package.pdf

Texas Instruments, PowerPAD Thermally Enhanced Package (SLMA002H). https://www.ti.com/lit/an/slma002h/slma002h.pdf

Renesas, package outline drawing M38.173C, 38-lead HTSSOP, MO-153 variation BDT-1. https://www.renesas.com/en/document/psc/package-drawing-tssop-ep-38pin-m38173c

Analog Devices, package drawing FE38 variation AA, 38-lead TSSOP with exposed pad (LTC DWG 05-08-1772 Rev C). https://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/ltc-legacy-tssop/tssop_38_05-08-1772.pdf

NXP, PCA9956B datasheet, HTSSOP38 exposed pad and thermal via requirements. https://www.nxp.com/docs/en/data-sheet/PCA9956B.pdf

[INTERNAL LINK: HTSSOP-28 thermal pad and land pattern -> HTSSOP-28 package guide]

[INTERNAL LINK: TSSOP-38 package dimensions -> TSSOP-38 outline and footprint guide]

[INTERNAL LINK: IPC-7351 land pattern density levels -> IPC-7351 naming and density level selection]

[INTERNAL LINK: reading JEDEC thermal metrics -> RthetaJA, psiJB and the JESD51 test boards]

[INTERNAL LINK: moisture sensitivity level handling -> MSL ratings, floor life and reflow profiles]