XC7Z020-1CLG400C
Dual-core ARM Cortex-A9 processing system fused with 28 nm Artix-7 programmable logic — one chip for software and gateware.
Key parameters
The most-searched attributes for the XC7Z020-1CLG400C, pulled together so you can qualify the part in seconds.
The XC7Z020-1CLG400C is a member of AMD's (formerly Xilinx) Zynq-7000 SoC family. It pairs a hardened dual-core ARM Cortex-A9 MPCore processing system (PS) — complete with NEON, floating-point, caches, DDR controller and a rich set of peripherals — with Artix-7 class programmable logic (PL) built on a 28 nm process. The two halves share a wide AXI interconnect, so software running on Linux or bare-metal can offload timing-critical or highly parallel work to custom logic on the same die.
A defining feature of the Zynq architecture is that the PS boots independently of the PL: the Cortex-A9 cores start executing immediately from QSPI, SD or NAND, and the FPGA fabric can be configured later or reconfigured at run time. That makes this device a strong fit for fast-boot embedded systems, industrial control, machine vision, motor drives, medical imaging, software-defined radio and edge-AI designs.
This specific ordering part carries the −1 speed grade (base performance, 667 MHz PS ceiling), the CLG400 package (400-ball chip-scale BGA, 17×17 mm) and the commercial temperature grade (C). Note the XC7Z020 has no gigabit transceivers or PCIe hard block — for serial links above LVDS rates, step up to the XC7Z015 or XC7Z030.
What the part number means
Every field in XC7Z020-1CLG400C encodes a decision. Here is how to read it — and how to jump to a neighbouring option.
XC7Z020 — device
Zynq-7000 SoC with 85K logic cells and Artix-7 PL. Siblings: Z010 (28K), Z015 (74K + transceivers), Z030 (125K).
−1 — speed grade
Base grade, 667 MHz PS. −2 lifts the ceiling to ~866 MHz, −3 to ~1 GHz. Same logic, higher timing & price.
CLG400 — package
400-ball wire-bond CSPBGA, 17×17 mm, 0.8 mm pitch. 100 PL user I/O. CLG484 gives the full 200 I/O.
C — temperature
Commercial, 0 °C to +85 °C junction. The …400I variant is industrial, −40 °C to +100 °C.
Technical specifications
Grouped by subsystem. Type in the filter to jump straight to a parameter — memory, DSP, I/O, voltage, whatever you need.
// Processing System (PS)
| Processor | Dual-core ARM Cortex-A9 MPCore |
| Max frequency (−1) | 667 MHz |
| Architecture | ARMv7-A, 2.5 DMIPS/MHz |
| FPU / SIMD | Double-precision FPU + NEON |
| L1 cache (per core) | 32 KB I + 32 KB D |
| L2 cache (shared) | 512 KB |
| On-chip memory (OCM) | 256 KB |
| Debug | CoreSight + PTM |
// Programmable Logic (PL)
| Fabric class | Artix-7, 28 nm |
| Logic cells | 85,000 |
| 6-input LUTs | 53,200 |
| Flip-flops | 106,400 |
| Slices | 13,300 |
| Distributed RAM | 1.06 Mb (max) |
| Clock mgmt tiles (CMT) | 4 (MMCM + PLL) |
| Gigabit transceivers | None |
// DSP & Analog
| DSP48E1 slices | 220 |
| DSP multiplier | 25 × 18 signed |
| Peak DSP (−1) | ~276 GMAC/s |
| XADC | 2× 12-bit, 1 MSPS |
| On-chip sensors | Temp + supply voltage |
| External analog inputs | Up to 17 channels |
// Block RAM
| Total block RAM | 4.9 Mb |
| 36 Kb blocks | 140 |
| Configurable as | 2× 18 Kb each |
| Port type | True dual-port |
| Max width | 72-bit |
// Memory & Peripheral interfaces
| DRAM controller | DDR3 / DDR3L / DDR2 / LPDDR2 |
| Static memory | 2× Quad-SPI, NAND, NOR |
| Ethernet | 2× tri-mode Gigabit |
| USB | 2× USB 2.0 OTG |
| SD / SDIO | 2× |
| UART / CAN | 2× UART, 2× CAN 2.0B |
| SPI / I²C | 2× SPI, 2× I²C |
| GPIO / DMA | 4× 32-bit GPIO, 8-ch DMA |
// Package, I/O & electrical
| Package code | CLG400 |
| Package type | 400-ball CSPBGA (wire-bond) |
| Body size | 17 × 17 mm |
| Ball pitch | 0.8 mm |
| PL user I/O (HR) | 100 |
| PS MIO | 54 |
| I/O standards | LVCMOS, LVDS, SSTL |
| VCCINT (core, −1) | 1.0 V |
| VCCAUX | 1.8 V |
| VCCO (I/O) | 1.2 V – 3.3 V |
| Junction temp (C) | 0 °C to +85 °C |
Resource fit estimator
Enter your target utilisation and see how much of the XC7Z020 fabric you would use. A quick sanity check before you commit to the part.
Estimator is a first-order guide only — real utilisation depends on your RTL, timing constraints and how the tools pack the fabric. Verify in Vivado.
Package & pinout
Everything you need to start a footprint and plan supply rails.
CLG400 package facts
- Type
- 400-ball CSPBGA
- Construction
- Wire-bond, lidless
- Body size
- 17 × 17 mm
- Ball pitch
- 0.8 mm
- Ball matrix
- 20 × 20
- PL user I/O
- 100 (HR banks)
- PS MIO
- 54
- Supply rails
- 7 primary
In CLG400, HR bank 33 is not bonded out and bank 13 is partially bonded — a key consideration if you later migrate to CLG484. Core rails must ramp before I/O rails per AMD's power-sequencing guidance.
Documents & downloads
The core reference set for designing in the XC7Z020. All documents are published by AMD.
Where to buy
Live stock and pricing from authorised distributors. Figures below are indicative — follow through for current quantities and price breaks.
| Distributor | Stock | Unit price (qty 1) | Price @ 500+ | Lead time | |
|---|---|---|---|---|---|
| DigiKey Authorised | In stock | $131.25 | ~$108 | Ships same day | View |
| Mouser Authorised | In stock | $131.25 | ~$110 | Ships same day | View |
| Avnet Authorised | Limited | $128.90 | ~$106 | 1–2 weeks | View |
| Newark / Farnell | In stock | $134.10 | ~$112 | Ships same day | View |
| Arrow | On order | $129.50 | ~$105 | Factory lead | View |
Indicative USD pricing for the commercial-grade part; distributors set live price, stock and break quantities. This device is NCNR (non-cancellable, non-returnable). Country of origin: Taiwan · ECCN EAR99 · HTS 8542.31.0070.
Alternatives & related parts
Same device in a different grade or package, or a family sibling with more (or fewer) resources.
| Part number | Change vs this part | Logic cells | Max PS | I/O | Temp | |
|---|---|---|---|---|---|---|
| XC7Z020-2CLG400C | Faster −2 speed grade | 85K | 866 MHz | 100 | Comm. | Compare |
| XC7Z020-1CLG400I | Industrial temperature | 85K | 667 MHz | 100 | Ind. | Compare |
| XC7Z020-1CLG484C | Full 200 I/O (larger BGA) | 85K | 667 MHz | 200 | Comm. | Compare |
| XC7Z010-1CLG400C | Smaller / lower-cost sibling | 28K | 667 MHz | 100 | Comm. | Compare |
| XC7Z015-1CLG485C | Adds gigabit transceivers | 74K | 667 MHz | 150 | Comm. | Compare |
| XC7Z030-1SBG485C | More logic + transceivers | 125K | 667 MHz | 150 | Comm. | Compare |
Dev boards using this device
Popular ways to get hands-on with the XC7Z020 before committing to a custom board.
Zybo Z7-20
Full-featured Zynq board with HDMI, audio and Pmod — the classic learning platform.
ZedBoard
Community reference board with FMC, wide peripheral set and huge project ecosystem.
PYNQ-Z2
Python-productivity board (PYNQ framework) for rapid overlays and edge experiments.
Cora Z7-10/20
Compact, low-cost Zynq board aimed at makers and embedded prototyping.
TE0720 module
Industrial SoM for dropping the XC7Z020 into a production carrier design.
STEMlab 125-14
Zynq-based instrumentation platform for RF, measurement and SDR work.
Frequently asked questions
Does the XC7Z020-1CLG400C have gigabit transceivers?+
What does the −1 speed grade mean vs −2 and −3?+
What temperature range does the trailing "C" mean?+
CLG400 vs CLG484 — which package should I choose?+
Which tools do I use to design with it?+
Is the part still in production and easy to source?+
XC7Z020-1CLG400C, Zynq and Xilinx are trademarks of AMD, used here for identification only. Technical data compiled from AMD DS190. Pricing and stock are indicative — verify with distributors before ordering. Last updated 09 Jul 2026.
