Post: Altera FPGA Guide: Series, Stock, Lead Times, and Quotes

An Altera FPGA is a field-programmable gate array from Altera Corporation — the same silicon that spent nine years badged as Intel FPGA. Intel bought Altera in 2015 for $16.7 billion, folded it into the Programmable Solutions Group, then spun it back out on January 1, 2025. Later that year Silver Lake took a 51% majority stake, with Intel keeping 49%. The devices did not change. Agilex, Stratix, Arria, Cyclone, and MAX 10 carry the same part numbers, the same pinouts, the same Quartus flow.

What changed is who supports them, who stocks them, and how long you wait. This guide covers the current Altera FPGA lineup, a selection process that starts with I/O rather than logic elements, what the supply chain actually looks like in 2026 — and the part most sourcing articles skip entirely: what a 2,000-ball Agilex package does to your stack-up, your fanout, and your reflow profile.

Key Takeaways for Engineers and Buyers

• Altera is independent again. Silver Lake holds 51%, Intel 49%. Documentation still says “Intel” in places (AN 114, AN 692); the parts are identical.
• Agilex, MAX 10, and Cyclone V now have availability planned through 2045 — with Agilex 7 M-Series devices carrying HBM2E memory explicitly excluded.
• Agilex uses numeric tiers: 3 (entry), 5 (mid-range), 7 (high-end), 9 (RF-grade). Stratix, Arria, and Cyclone are the legacy three-tier lineup.
• Ball pitch is not what forces you into HDI. Board thickness and drill aspect ratio are. A 1.0 mm-pitch package on a thick backplane can still break a 10:1 PTH limit.
• FPGAs are among the most counterfeited components on the market. If you buy outside the authorized channel, budget for X-ray, XRF, decapsulation, and a JTAG IDCODE check before those parts touch a stencil.

What Is an Altera FPGA, and Who Actually Owns Altera Now?

An Altera FPGA is a reprogrammable logic device: a grid of adaptive logic modules (ALMs), DSP blocks, embedded RAM, and hard I/O, stitched together by a configurable routing fabric. You describe the circuit in Verilog, VHDL, or C/C++ through high-level synthesis, compile it in Quartus Prime, and load the resulting bitstream at power-up. Change the bitstream, change the circuit. No mask set, no NRE, no eighteen-month tapeout.

The ownership question comes up constantly because it breaks approved-vendor lists. Altera was founded in 1983 — the name is a play on “alterable” — and went public in 1988. Intel acquired it in December 2015. In October 2023 Intel announced it would spin the unit out; the Altera name returned in February 2024; the company became an independent subsidiary on January 1, 2025; and in 2025 Silver Lake acquired majority ownership.

The practical consequence for you: documentation lives in two namespaces. Application notes such as AN 114 (board design guidelines for programmable device packages) and AN 692 (power sequencing) still carry Intel branding and intel.com URLs. Datasheets, PCNs, and end-of-life notices now come from Altera. Part numbers never moved — an EP4CE22, a 10M08, a 5CSEBA6 all resolve to the same die they always did. If your ERP system lists Intel as the manufacturer of record on a Cyclone IV, that is a data-hygiene problem, not a sourcing problem, but it will absolutely trip an AVL audit.

Most modern Altera devices ship in both a plain FPGA variant and an SoC variant with a hard Arm processor system on-die. Cyclone V and Arria 10 SoCs use a dual-core Cortex-A9. Stratix 10 and Agilex 7 SoCs use a quad-core Cortex-A53. Agilex 5 SoCs use a Cortex-A76/A55 combination; Agilex 3 SoCs use a dual-core Cortex-A55. If you need a processor but not a hard one, Altera now points you at Nios V, a RISC-V soft core that has replaced the older proprietary Nios II.

Altera FPGA Series Compared: Agilex 3, 5, 7, 9 vs Cyclone, MAX 10, Arria, and Stratix

For roughly two decades Altera sold three tiers by name: Stratix on top, Arria in the middle, Cyclone at the bottom, with the non-volatile MAX family off to one side. Agilex threw that out. It grades by number — the higher the number, the higher the tier — and the numbering is not a generation counter. Agilex 7 is not newer than Agilex 5; it is bigger.

Family	Tier	Logic capacity	Transceivers / high-speed I/O	Hard processor	Typical application	Availability
Agilex 9	RF-grade flagship	High-end	Integrated data converters, sampling up to 64 Gbps	Optional SoC	Radar, electronic warfare, software-defined radio	Through 2045
Agilex 7	High-end	600K–4.1M LE	32G NRZ, 56G and 112G PAM4; NoC; HBM2E on M-Series	Cortex-A53 quad (SoC)	Data center, optical transport, 5G	Through 2045 except HBM2E parts
Agilex 5	Mid-range	Mid	Multi-gigabit SerDes, MIPI, industrial Ethernet; AI Tensor Blocks in fabric	Cortex-A76/A55 quad (SoC)	Edge AI, machine vision, robotics	Through 2045
Agilex 3	Entry / cost-optimized	25K–135K LE	PCIe 3.0 x4, 10 GbE	Cortex-A55 dual (SoC)	Sensor bridging, control, instant-on logic	Through 2045
Stratix 10	Legacy high-end	High	Up to 57.8 Gbps; Hyperflex register architecture	Cortex-A53 quad (SoC)	Optical transport, HPC, high-frequency trading	Long-life legacy
Arria 10	Legacy mid-range	Mid	Up to 17.4 Gbps	Cortex-A9 dual (SoC)	Video processing, 5G, medical imaging	Long-life legacy
Cyclone V	Cost-optimized	Low to mid	Multi-gigabit SerDes on GX/GT variants	Cortex-A9 dual (SoC)	Industrial control, robotics, DE10-Nano class boards	Through 2045
MAX 10	Non-volatile	2K–50K LE	None	None	Power sequencing, glue logic, config manager, instant-on	Through 2045

Table 1. Altera FPGA families at a glance. “LE” = logic elements. Availability reflects Altera’s April 2026 lifecycle announcement; legacy families remain supported but were not part of that specific extension.

In April 2026 Altera extended planned availability for the Agilex, MAX 10, and Cyclone V families through 2045 — a 19-year runway from today. The announcement carries two footnotes worth reading before you design one in: Agilex 7 devices with integrated HBM2E memory are excluded, because high-bandwidth memory has a shorter lifecycle than the FPGA it sits beside; and the commitment is subject to the usual force majeure around vendor discontinuance and tool obsolescence. Full text is at Altera’s lifecycle press release.

That 2045 date is the single most useful sourcing fact Altera has published since the spin-off. If you build medical, rail, industrial, or defense equipment that has to survive a 15-year field life and a recertification cycle, an obsolescence notice is not a purchasing inconvenience — it is a six-figure redesign plus requalification. A published 2045 horizon on MAX 10 and Cyclone V is why those two parts keep showing up on new schematics that could technically use something newer.

Two family-specific notes that change board architecture. MAX 10 carries internal flash, which means it configures itself — no external EPCQ configuration device, one fewer BOM line, and no boot-time race between the FPGA and whatever it is supposed to be supervising. That makes MAX 10 the default choice for power sequencing and board management even on boards whose main compute is a large Agilex. And Agilex 5 places AI Tensor Blocks directly in the fabric, which is why it keeps winning edge-inference sockets that would otherwise need a separate accelerator.

How to Choose an Altera FPGA: A Five-Step Selection Process

Engineers pick FPGAs by logic-element count. Buyers then discover the package is a 2,000-ball monster at 1.0 mm pitch and the board cost doubles. Run the selection in this order instead.

1. Count the interfaces before the logic. Add up your DDR channels, PCIe lanes, Ethernet ports, MIPI lanes, and general-purpose I/O. High-speed interfaces consume hard IP tiles and physical pins, and pins drive package size, and package size drives layer count. Logic elements are the cheapest thing on the list to add later — pins are not.
2. Set the transceiver ceiling. Anything at or above 25 Gbps per lane is Agilex 7 or Stratix 10 territory and pulls low-loss laminate and back-drilling into your fab spec. Anything at 10 Gbps or below can usually live on Agilex 5 or Arria 10 with a well-designed stack-up on a mid-Tg FR-4.
3. Decide hard processor versus soft core. A hard Cortex-A gives you Linux, a memory controller, and a boot ROM you did not have to build. A Nios V soft core on RISC-V costs fabric and clock rate but survives device migrations. If your firmware team wants a package manager, take the hard processor.
4. Verify the toolchain and license before you commit. Quartus Prime Lite (free, no license) covers MAX 10, Cyclone V, and Cyclone 10 LP. Standard covers older families such as Stratix V and Arria V. Pro Edition is required for Agilex, Stratix 10, Arria 10, and Cyclone 10 GX — but Agilex 3, Agilex 5, and Cyclone 10 GX can use Pro at no cost, and Agilex 5 E-Series has a dedicated no-cost license (SW-AGILEX-5E). The current release is Quartus Prime Pro 26.1. Nothing derails a schedule quite like discovering in week six that your device needs a paid seat.
5. Price the board, not just the part. This is where selection goes wrong most often — see below.

Here is the truth about step five: the cheapest die frequently produces the most expensive assembly. A MAX 10 in a 0.5 mm-pitch package is a few dollars of silicon, but 0.5 mm pitch forces via-in-pad, which forces laser-drilled microvias, which forces an HDI build — and HDI typically adds 15% to 25% to bare-board cost while roughly doubling fab lead time. The same design in a 1.0 mm-pitch package on a standard 8-layer through-hole build may cost more in silicon and less in total. Ask for both quotes before you freeze the schematic.

Altera FPGA Stock, Lead Times, and the Authorized vs Independent Distributor Trade-off

There are three ways to buy an Altera FPGA, and they carry three completely different risk profiles.

Channel	Traceability	Typical lead time	Price	What you must do yourself
Authorized / franchised distributor	Full: manufacturer certificate of conformance, lot and date codes, unbroken chain of custody	Off-the-shelf to 40+ weeks depending on device	List	Nothing beyond incoming goods inspection
Independent / open-market distributor	Varies. Look for AS9120 QMS and documented AS6081 counterfeit-avoidance procedures	Days to weeks	1x to 5x list on scarce parts	X-ray, XRF, decapsulation on a sample, JTAG IDCODE verification, first-article build
Excess inventory from another OEM	Sometimes excellent, sometimes a bin of unknown reels	Immediate	Below list to well above	Everything above, plus moisture-sensitivity level (MSL) requalification and bake

Table 2. Altera FPGA sourcing channels compared. Lead times are indicative and move constantly — treat them as a starting point for a quote, not a specification.

FPGAs sit near the top of every counterfeit-risk list published in the last fifteen years, for a simple reason: high unit value, long field life, and a steady stream of obsolete part numbers that authorized channels no longer stock. Remarked parts, resurfaced parts, recovered parts pulled off scrapped boards, and outright empty packages all circulate. The Government-Industry Data Exchange Program (GIDEP) exists precisely because this happens often enough to need a reporting system.

Two verification checks catch most of what gets through, and neither is expensive. First, X-ray the lot and compare die outline and bond-wire pattern across samples — a mixed lot shows up immediately. Second, power up a sample and read the JTAG IDCODE. Every Altera device returns a device-specific identifier over boundary scan; a Cyclone IV that reports the wrong IDCODE never gets near a stencil. Add XRF for lead-free marking verification and decapsulation on one unit per date code if the application is safety-critical.

Now the honest trade-off. Suppose an authorized distributor quotes 38 weeks on a legacy Arria 10 and an independent quotes two weeks at 3x list. On a 500-unit build with a $180 device, the broker premium is roughly $180,000 — hard to swallow. On a 40-unit build of a $180 device, the premium is about $14,400, and eight months of schedule slip on a medical product costs far more than that. The correct answer depends entirely on volume and on what the delay costs. Budget an extra $800 to $2,000 for authentication testing on any open-market lot and make the comparison on total landed cost, not on unit price.

One more thing procurement teams routinely get wrong: “authorized distributor” is a claim anyone can put on a website. Verify it against the ECIA membership list or the manufacturer’s own where-to-buy page. A company that ranks highly on Google for the phrase is not thereby authorized.

PCB Design Rules for Altera FPGA BGA Packages: Stack-Up, Fanout, and Impedance

Every production Altera FPGA above the MAX 10 class ships in a ball grid array. Once your device selection is locked, the package geometry writes most of your fabrication spec for you. Work through it in this order: pad, fanout, via, aspect ratio, layer count, impedance.

Ball pitch	Fanout method	Via technology	Fab technology required	Relative bare-board cost
1.27 / 1.0 mm	Dog-bone	Plated through-hole	Standard multilayer	Baseline
0.8 mm	Dog-bone (tight)	PTH, roughly 0.2 mm drill	Standard multilayer, controlled etch	Baseline +10%
0.65 mm	Mixed dog-bone / via-in-pad	Filled and capped via-in-pad	HDI 1+N+1 or sub-lamination	+15% to +25%
0.5 mm	Via-in-pad	Laser microvia, copper-filled	HDI 2+N+2	+25% to +40%
0.4 mm and below	Via-in-pad only	Stacked or staggered microvias	HDI 3+N+3, tight registration	+40% and up

Table 3. BGA ball pitch drives fab technology. Prefer staggered microvias over stacked wherever routing allows — staggered structures have measurably better thermal-cycling reliability.

Now the part that surprises people. Pitch is not what forces you into HDI. Aspect ratio is.

Take a large Agilex package at a comfortable 1.0 mm pitch, sitting on a 2.4 mm-thick backplane because you needed twenty layers and a 3 oz power plane. Fanout wants a 0.2 mm finished drill. That is a 12:1 aspect ratio, and most fabricators cap reliable through-hole plating at 10:1 — some at 8:1 for IPC-6012 Class 3. You are now in a sub-lamination or blind-via build on a package that, by pitch alone, looked like a standard through-hole job. Meanwhile a 0.65 mm-pitch part on a 1.0 mm-thick 8-layer board may fan out with ordinary mechanical drilling. Check thickness divided by drill diameter before you conclude anything from the pitch table.

Practical geometry, in numbers you can hand to a layout engineer. Copper pad diameter runs 0.8 to 0.9 times the solder ball diameter. Use non-solder-mask-defined (NSMD) pads — copper etch registration is tighter than solder mask registration, and NSMD exposes more copper for the ball to wet. Solder mask opening should be 0.05 to 0.1 mm larger than the pad. Where via-in-pad is unavoidable, the via must be copper-filled and planarized (plated-over filled via), not merely tented; an unfilled via in a BGA pad wicks solder off the joint and produces exactly the kind of intermittent open that survives ICT and fails in the field.

For transceiver lanes, the two levers are laminate and stub length — and engineers routinely reach for the expensive one first. Standard FR-4 at 10 GHz has a dissipation factor around 0.02 and a stripline insertion loss on the order of 0.7 to 1.0 dB per inch. A low-loss laminate such as Panasonic Megtron 6 drops Df to roughly 0.002 and insertion loss to roughly 0.2 to 0.4 dB per inch. That upgrade is real and it is expensive. But an un-back-drilled via stub of 1.3 mm on a 25 Gbps lane can eat more margin than the laminate ever gives back, and back-drilling to leave a stub under 0.25 mm costs a fraction of a material change. Model the channel, then spend.

Two more items that belong in the fab notes, not the design review. Specify controlled impedance explicitly: 50 ohms single-ended and 100 ohms differential is standard, with ±10% tolerance under IPC-6012 Class 2. Tightening to ±5% is achievable but requires the fabricator to adjust dielectric thickness or trace width per lot, and it will show up on the quote. And follow AN 692 on power sequencing: VCCINT must be stable before the VCCIO rails come up on most Altera families. Get sequencing wrong and the device does not fail loudly — it draws excess current, heats, and configures intermittently, which is a genuinely miserable thing to debug at 2 a.m.

Assembling Altera FPGA Boards: Reflow Profile, Package Warpage, and X-Ray Inspection

A large Agilex or Stratix package is one of the harder SMT placements in the industry. It is physically big, thermally massive, and it warps. The board underneath it also warps, in the opposite direction, at a different rate. Everything below follows from that.

With SAC305 paste, liquidus is 217°C. Target a peak of 235°C to 245°C at the coldest joint, with time above liquidus of 45 to 90 seconds. On a board carrying a 2,000-ball FPGA plus 0402 passives, the delta between the hottest and coldest thermocouple is the number that matters — not the peak. If you cannot hold that delta under about 10°C, you profile for the corner balls of the FPGA and accept a slightly hotter chip resistor, not the other way round.

Here is a counterintuitive one that costs people money: a slower ramp is not automatically safer. Ramping too slowly through the soak lets the flux volatiles boil off before the joint collapses, which sounds good, but it also gives the package more time at the temperature where warpage peaks. On large-body FPGAs the corner balls lift, the paste does not coalesce, and you get head-in-pillow — a joint that looks perfect on X-ray at first glance because the ball is round and the paste is round, and they are simply not fused.

A machine-vision OEM we worked with shipped roughly 5,000 industrial camera boards built around a 672-ball, 0.8 mm-pitch Cyclone V SoC on a 10-layer stack-up. Every unit passed AOI, ICT, and functional test. Field returns started at about seven months, running near 1.2%, clustered in units deployed near furnace lines. Dye-and-pry on returned boards showed head-in-pillow on four corner balls and nothing else. The fix was unglamorous: step the stencil from 0.10 mm to 0.13 mm over the outer two ball rows, add nitrogen to the reflow oven, and trim ten seconds off the soak. Yield loss on the reworked line went to zero. Nobody had to change the layout.

Inspection is not optional under a BGA — you cannot see the joints. Use automated X-ray to check for voiding, bridging, and missing balls; most EMS acceptance limits sit at 25% to 30% void area per ball, consistent with IPC-7095 guidance. Boundary scan (JTAG) verifies connectivity through the FPGA’s own test logic and catches opens that X-ray cannot. Combine the two. AOI handles everything you can see; it tells you nothing about the part that matters.

Finally, agree the acceptance class up front. IPC-A-610 Class 2 is the default for commercial equipment; Class 3 is for products where failure is not an option — medical, avionics, life support — and Class 3 changes solder joint criteria, annular ring requirements under IPC-6012, and workmanship standards under J-STD-001. Class 3 is not “better quality” in some abstract sense. It is a different set of measurable acceptance criteria, and it costs more because more boards fail them.

Common Altera FPGA Design and Sourcing Mistakes

These are the ones that show up repeatedly in DFM review — the send-this-to-a-junior-engineer list.

• Selecting the device on logic elements and discovering the pin count later. Interfaces drive pins, pins drive the package, the package drives the board.
• Assuming ball pitch alone determines whether you need HDI. Divide finished board thickness by finished drill diameter first.
• Using tented rather than copper-filled vias in BGA pads. Solder wicks down the barrel and you get an intermittent open that passes ICT.
• Specifying “controlled impedance” in the fab notes without a target, a tolerance, or a stack-up drawing. The fabricator will guess, and the guess will be ±10%.
• Buying a low-loss laminate before back-drilling the via stubs. Stub resonance is usually the bigger loss term below 30 GHz, and it is cheaper to fix.
• Ignoring AN 692 power sequencing. VCCINT before VCCIO on most families. Intermittent configuration failures trace back here more often than to the bitstream.
• Treating a broker’s “in stock” as equivalent to a franchised distributor’s stock. Verify against the ECIA list, then X-ray and read the JTAG IDCODE anyway.
• Designing in an Agilex 7 M-Series part with HBM2E on a 20-year platform. The FPGA is supported through 2045; the high-bandwidth memory is not.
• Sending Gerbers with no stack-up, no impedance table, and no IPC class, then asking why the quote came back with a two-week clarification loop.

Five Things to Do This Week

1. Pull your finished board thickness and smallest finished drill from the current stack-up and compute the aspect ratio. If it exceeds 10:1, escalate to your fabricator now, not at Gerber release.
2. Check every Altera part on your BOM against Altera’s lifecycle status, and flag anything that is not Agilex, MAX 10, or Cyclone V for a second-source review.
3. Confirm which Quartus edition and license your target device needs before the FPGA team writes a line of RTL. Agilex 5 E-Series has a no-cost Pro license; Agilex 7 does not.
4. Add an incoming-inspection line item to any purchase order placed outside the authorized channel: X-ray, XRF, and a JTAG IDCODE read on one unit per date code.
5. Export the design in IPC-2581 or ODB++ rather than bare Gerber. The stack-up, netlist, and impedance requirements travel with the data instead of living in a PDF nobody opens.

Frequently Asked Questions About Altera FPGAs

Is Altera still owned by Intel?

No, not majority-owned. Intel acquired Altera in 2015 and spun it back out as an independent subsidiary on January 1, 2025. In 2025 the private equity firm Silver Lake acquired a 51% majority stake, leaving Intel with 49%. Altera now operates as an independent pure-play FPGA company headquartered in San Jose.

Is an Altera FPGA the same as an Intel FPGA?

Yes. Between 2015 and 2024 the same devices were marketed as Intel FPGA under the Programmable Solutions Group. Agilex, Stratix, Arria, Cyclone, and MAX parts kept their part numbers throughout. If a datasheet, application note, or reference design says Intel FPGA, it describes the identical silicon you would buy today as Altera.

Which Altera FPGA families are supported through 2045?

In April 2026 Altera extended planned availability for the Agilex series, MAX 10, and Cyclone V — FPGAs and SoC variants alike — through 2045. Agilex 7 devices with integrated HBM2E memory are excluded, because the memory has a shorter lifecycle than the FPGA. Legacy families such as Stratix 10 and Arria 10 remain supported under their own schedules.

Is Quartus Prime free for Altera FPGAs?

Partly. Quartus Prime Lite is free and covers MAX 10, Cyclone V, and Cyclone 10 LP. Pro Edition is required for Agilex, Stratix 10, and Arria 10, and normally needs a paid license — but Agilex 3, Agilex 5, and Cyclone 10 GX can use Pro at no cost. Agilex 5 E-Series has a dedicated free license, SW-AGILEX-5E.

What should replace an obsolete Cyclone IV or Cyclone III design?

Cyclone V is the low-friction migration: same tool family, comparable I/O structures, and availability planned through 2045. If the design needs a processor, the Cyclone V SoC adds a dual-core Cortex-A9. For fresh designs at similar density, Agilex 3 offers a Cortex-A55, PCIe 3.0 x4, and 10 GbE on a modern process.

How do you tell whether an Altera FPGA is counterfeit?

Run four checks. X-ray the lot and compare die outline and bond-wire patterns across samples. Read the JTAG IDCODE on a powered sample and confirm it matches the marked device. Use XRF to verify the marking and lead finish. Decapsulate one unit per date code if the application is safety-critical. Mismatched date codes within a reel are an immediate red flag.

Do all Altera FPGA boards need an HDI PCB?

No. Ball pitch at or above 0.8 mm generally fans out with dog-bone routing and plated through-holes on a standard multilayer build. HDI becomes necessary around 0.65 mm and below, or whenever board thickness divided by drill diameter exceeds roughly 10:1. Many large Agilex packages use 1.0 mm pitch specifically to avoid forcing HDI.

How many layers does an Altera FPGA board need?

It depends on signal pin count, not total pin count. A 400-ball device at 0.5 mm pitch with about 60% signal pins typically needs four escape-routing layers plus two to four reference planes — call it eight to ten layers. Large Agilex 7 designs with multiple transceiver banks routinely run sixteen to twenty-four.

Get Your Altera FPGA Board Quoted: Gerber, BOM, and a DFM Review

Choosing an Altera FPGA is a two-part decision, and most teams only make the first half consciously. The device selection settles logic, transceivers, and toolchain. The package selection quietly settles your via technology, your layer count, your laminate, your reflow window, and about a third of your unit cost. Agilex, Cyclone V, and MAX 10 now come with a 2045 availability horizon, which removes the obsolescence question from the equation — but it does not tell you whether your 0.65 mm-pitch fanout will pass a 10:1 aspect-ratio check, and it does not tell you whether the reel a broker is offering came out of a factory or out of a scrapped chassis.

Both of those are answerable before you spend money on a build. Send your Gerber or IPC-2581 package, your stack-up, and your BOM for a DFM review and quote, and we will come back with the aspect ratio, the fanout strategy, the impedance stack-up, and a straight answer on lead time.