FPGA designs push printed circuit board fabrication harder than almost any other class of digital hardware. A single large FPGA can bring hundreds of high-speed lanes, multiple DDR memory interfaces, dedicated transceivers running at tens of gigabits per second, and a power tree that has to feed a dozen or more voltage rails, all escaping from one enormous ball grid array. Getting that onto a manufacturable board means high layer counts, tight impedance control, advanced via structures and careful material selection, none of which a generic quick-turn fab is built to handle well.
FPGA.io specialises in FPGA PCB fabrication for exactly this reason. Whether you are spinning a first prototype of an AMD (Xilinx), Altera, Lattice or Microchip design or scaling a proven board into volume, this page explains what makes FPGA boards difficult to fabricate, the capabilities you should expect from your fabricator, and how to get your design built right the first time.
Why FPGA boards are harder to fabricate than ordinary PCBs
Most two- and four-layer boards are forgiving. FPGA boards are not. Four characteristics separate them from routine work, and each one raises the bar on the fabrication process.
- High layer counts. Escaping a large BGA, separating dozens of signal groups, and giving every power rail a clean plane usually forces the stackup to 8, 12, 16 or more layers. Bonding that many layers with consistent registration and reliable plating is a different manufacturing discipline than pressing a simple four-layer board.
- Controlled impedance everywhere. DDR3/DDR4/DDR5 buses, LVDS pairs, and multi-gigabit transceiver links only work if the copper geometry and dielectric are held to tight tolerances. Impedance targets of 40, 50, 90 and 100 ohms must be met within a few percent across the whole panel.
- Dense escape routing. A fine-pitch BGA can have well over a thousand balls on a 0.8 mm or 0.4 mm grid. Fanning those signals out of the array often requires laser-drilled microvias and high-density interconnect (HDI) construction rather than plain through-holes.
- A demanding power and thermal profile. Large FPGAs draw significant current in bursts, so planes carry heavy copper, and the board has to spread heat away from a device that can dissipate tens of watts.
The practical takeaway is simple: an FPGA board that a low-cost prototype house builds “successfully” can still fail on the bench because of impedance drift, plating voids in a buried via, or a stackup that never met the design’s signal-integrity assumptions. A fabricator that understands FPGA PCB assembly and high-speed design as a whole is worth far more than the cheapest per-panel price.
FPGA PCB fabrication capabilities
The table below shows the fabrication envelope we build FPGA boards within. If your design sits inside these limits, it is manufacturable with high yield; if it pushes past them, our engineers will flag it during the free DFM review before anything goes to production.
| Fabrication parameter | Capability |
| Layer count | 1 to 40+ layers |
| Board thickness | 0.2 mm to 6.0 mm |
| Base material | FR-4, mid-loss and low-loss high-speed laminates, Rogers, polyimide, metal-core |
| Minimum trace width / spacing | 3 mil / 3 mil (2.5 mil on HDI) |
| Minimum mechanical drill | 0.15 mm |
| Minimum laser microvia | 0.075 mm |
| Impedance tolerance | +/- 10% standard, +/- 5% on request |
| Copper weight | 0.5 oz to 6 oz (heavy copper available) |
| Surface finish | ENIG, ENEPIG, immersion silver, immersion tin, OSP, hard gold, HASL |
| Via types | Through-hole, blind, buried, stacked/staggered microvia, via-in-pad |
| Quality class | IPC-A-600 Class 2 and Class 3 |
| Certifications | ISO 9001, UL, RoHS/REACH compliant |
Choosing the right laminate for high-speed FPGA designs
Material selection is where signal integrity is won or lost. Standard FR-4 is inexpensive and perfectly adequate for lower-speed logic, but its dielectric loss rises with frequency, which degrades multi-gigabit links and long DDR routes. For transceiver-heavy FPGA designs, a mid-loss or low-loss laminate keeps insertion loss and jitter under control.
In practice we help teams place their design on the loss/cost curve:
- Standard FR-4 for control logic, slower interfaces, and cost-sensitive boards where the fastest lanes stay short.
- Mid-loss laminates for DDR4-class memory and moderate serial-link speeds, giving a large signal-integrity improvement for a modest cost increase.
- Low-loss and ultra-low-loss systems (such as Megtron-class or Rogers materials) for 16 Gbps-plus transceivers, high lane counts, or long backplane runs.
Dielectric constant (Dk) stability, glass-weave style, and copper roughness all matter here too, because they influence both impedance repeatability and high-frequency loss. We match the laminate to the fastest interface your FPGA actually uses, rather than over-specifying an expensive stackup you do not need.
Layer stackup design for signal integrity
A good stackup does three jobs at once: it gives every high-speed net a solid, adjacent reference plane; it delivers low-inductance power to the FPGA; and it keeps coupling between signal layers under control. On a dense FPGA board those goals compete for layers, so the stackup is a deliberate engineering decision, not an afterthought.
Our fabrication team will review or co-develop your stackup to confirm that impedance targets are achievable with real, available core and prepreg thicknesses, that plane pairs are positioned for good decoupling, and that the symmetric build will not warp during reflow, a genuine risk when a heavy BGA is later placed during assembly. Sending an unbuildable stackup to fabrication is one of the most common causes of a re-spin, and it is entirely avoidable.
Via technology: through, blind, buried, microvia and via-in-pad
Vias are the quiet workhorses of an FPGA board, and the escape from a fine-pitch BGA usually dictates which via technologies you need.
- Plated through-holes are the default and the lowest cost, but they consume routing space on every layer they pass through.
- Blind and buried vias connect only the layers that need connecting, freeing up routing channels, which is often the only way to escape a dense array without exploding the layer count.
- Laser-drilled microvias, stacked or staggered, are the enabling technology for HDI boards and for fanning signals out from 0.5 mm and 0.4 mm pitch BGAs.
- [Via-in-pad](https://en.wikipedia.org/wiki/Via_in_pad) places the via directly in the component pad. It is frequently unavoidable under fine-pitch BGAs, but it must be filled and capped (plated over) so that solder does not wick down the barrel during assembly, a defect that is expensive to find and worse to ship.
Choosing the right mix keeps the board reliable and manufacturable. We treat via strategy as part of the DFM conversation, not a checkbox at the end.
Surface finishes, and why ENIG matters for BGAs
The surface finish protects the exposed copper and determines how well fine-pitch parts solder. For FPGA boards dominated by ball grid array packages, the finish is not a cosmetic choice.
ENIG (Electroless Nickel Immersion Gold) is the workhorse finish for BGA-heavy boards. It gives a flat, planar surface, which matters enormously when you are placing a large BGA with a thousand-plus balls, and it offers a long shelf life and excellent solderability. ENEPIG adds a palladium layer for wire-bonding and mixed-technology needs. Immersion silver and OSP are lower cost and work well for many designs, while HASL is generally avoided under fine-pitch BGAs because its uneven surface makes reliable placement harder. When in doubt on an FPGA board, ENIG is the safe default, and we will tell you when a cheaper finish is genuinely fine.
Impedance control and electrical testing
Meeting an impedance target on paper is not the same as meeting it on the panel. We build to your impedance requirements using field-solver-verified stackups, then verify the result. Every controlled-impedance FPGA board can be shipped with time-domain reflectometry (TDR) coupon data so you have measured proof, not just a promise, that the DDR bus and transceiver lanes are within tolerance.
Beyond impedance, 100% electrical net testing (flying-probe for prototypes, fixtured testing for volume) confirms there are no opens or shorts before the board ever reaches assembly. Catching a fabrication defect at the bare-board stage costs a fraction of finding it after expensive FPGAs and memory have been placed.
Quality, inspection and certifications
FPGA boards are typically built to IPC Class 2 for commercial products or Class 3 for high-reliability applications in aerospace, defence, medical and industrial control. Class 3 tightens annular ring, plating thickness, and acceptance criteria across the board.
Our fabrication quality process includes automated optical inspection (AOI) of inner and outer layers, microsection analysis to verify plated-hole and via quality, controlled-impedance coupon testing, and final electrical test. Boards are manufactured under an ISO 9001 quality system with UL recognition and full RoHS/REACH compliance. If your program requires specific documentation, certificates of conformance, microsection reports, or impedance data, we supply it with the shipment.
From prototype to volume production
The same design should not be built two different ways at two different vendors. Fabricating your prototypes and your production boards on one line, to one qualified stackup, removes a major source of “it worked on the prototype” surprises. We support the full lifecycle: fast-turn prototypes to get your FPGA design onto the bench quickly, a bridge stage for pilot runs and design validation, and volume production with consistent processes and stable lead times. Because sourcing scarce FPGAs and long-lead parts is often the real bottleneck, our component sourcing team can run in parallel so the bare boards and the parts arrive together.
Frequently asked questions
How many layers does an FPGA board usually need?
It depends on the device and the interfaces, but mid-size FPGA designs commonly land between 8 and 14 layers, and large designs with many transceivers and DDR channels can require 16 or more. The layer count is driven mainly by BGA escape routing and the number of power and reference planes you need.
Do I need controlled impedance for my FPGA board?
Almost always. Any DDR memory interface, LVDS pair, or serial transceiver link relies on a specific characteristic impedance to function. If your design has any of these, controlled-impedance fabrication is not optional.
Can you build boards with via-in-pad under the BGA?
Yes. We routinely build filled and capped via-in-pad structures under fine-pitch BGAs. Proper filling and planarisation is essential so that solder does not escape down the via during BGA assembly.
What surface finish should I choose for a large FPGA?
ENIG is the recommended default for BGA-dominated FPGA boards because of its flat surface and reliable solderability. We will suggest a lower-cost alternative only when your design allows it.
Can you fabricate and assemble the board together?
Yes. FPGA.io offers turnkey fabrication plus assembly, including BGA assembly and component sourcing, so one team owns the board from bare copper to a tested, populated assembly.
Get an FPGA-grade fabrication quote
Send us your Gerber or ODB++ files and stackup and we will return a fabrication quote, typically within 24 hours, along with a free manufacturability review that flags any issues before they cost you a re-spin.
Related services: PCB Assembly | BGA Assembly | Component Sourcing | Free DFM Review
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