TVSOP (Thin Very Small Outline Package) is a Texas Instruments-developed, JEDEC MO-194-registered surface-mount package with a 0.40 mm lead pitch and a 1.2 mm max height, available in 14-, 16-, 20-, 24-, 48-, 56-, 80-, and 100-pin variants. It was built to hit the 1.2 mm PCMCIA card-height limit and remains, for select current parts, an Active option today — though most designers reach for QFN or BGA instead.

Key takeaways

• TVSOP uses a 0.40 mm pitch — finer than TSSOP’s 0.5/0.65 mm — inside a body that’s roughly 30–62% smaller in area than the equivalent SSOP or TSSOP part, depending on pin count.
• It’s registered under JEDEC MO-194 (not MO-153, TSSOP’s standard), though the exact variation letter changes by pin count.
• Lifecycle status is genuinely mixed, not uniformly obsolete: some current TI logic parts in TVSOP are marked Active as recently as an April 2026 package addendum, others are NRND, and IDT (now Renesas) discontinued dozens of TVSOP logic parts back in 2001–2002.
• In a direct TI 48-pin comparison, TVSOP actually beat TSSOP and SSOP on simultaneous-switching noise and propagation-delay degradation — smaller isn’t just about board space here.
• At 0.40 mm pitch, component placement precision matters far more than with TSSOP — TI’s own data shows defect rates climbing up to 30x for widely-spaced parts placed with the wrong lead orientation.

Dimensions by Pin Count

TI’s own application report gives typical dimensions for all eight TVSOP pin-count variants, along with how much smaller each is than the equivalent SSOP and TSSOP part:

Pins	Body length (mm)	Body width (mm)	Lead-tip span (mm)	Area (mm²)	Smaller than SSOP	Smaller than TSSOP
14	3.60	4.40	6.40	23.0	52.4%	29.3%
16	3.60	4.40	6.40	23.0	52.4%	29.3%
20	5.00	4.40	6.40	32.0	43.0%	24.0%
24	5.00	4.40	6.40	32.0	50.0%	34.0%
48	9.80	4.40	6.40	63.0	61.9%	38.0%
56	11.3	4.40	6.40	72.3	62.2%	36.0%
80	17.0	6.10	8.10	137.8	— (30% smaller than TQFP)	—
100	20.8	6.10	8.10	168.5	— (35% smaller than TQFP)	—

Lead pitch is 0.40 mm across the entire family, and max height is 1.20 mm across all eight variants. Note the same body-width pattern you’d recognize from TSSOP — a 4.40 mm body for lower pin counts, a wider 6.10 mm body once pin count climbs — except TVSOP switches to the wider body at 80 pins, not at the same threshold TSSOP uses.

JEDEC Registration

TVSOP packages are registered under JEDEC MO-194, with a distinct variation letter per pin count and TI package-code designator:

TI package code	Pins	JEDEC registration	Body family
DGV	14	MO-194AA	Narrow (4.40mm)
DGV	16	MO-194AB	Narrow (4.40mm)
DGV	20	MO-194AC	Narrow (4.40mm)
DGV	24	MO-194AD	Narrow (4.40mm)
DGV	48	MO-194AE	Narrow (4.40mm)
DGV	56	MO-194AF	Narrow (4.40mm)
DBB	80	MO-194BA	Wide (6.10mm)
DBB	100	MO-194BB	Wide (6.10mm)

Where TVSOP Actually Came From — and Whether It’s Still Available

TVSOP’s defining constraint — a 1.2 mm max height — wasn’t arbitrary. It was engineered to meet the PCMCIA (PC Card) height requirement, back when laptop expansion cards were a real market. That market is long gone, which raises the obvious question: is this package still usable in a new design?

The honest answer is mixed, and worth checking per part rather than assuming either way:

• IDT (now part of Renesas) issued Product Discontinuance Notice PDN LOGIC-01-01 on January 29, 2001, discontinuing dozens of FCT and FST logic parts in the TVSOP (PF) package — last-ship date April 28, 2002 — citing obsolete package/material as the reason, with no replacement part numbers offered.
• Texas Instruments, the package’s originator, has not walked away from it entirely. Package option addenda checked directly on ti.com show real current status: SN74CB3T3245DGVR (bus switch, 20-pin) is listed Active/Production as of an April 29, 2026 addendum; SN74AHC573DGVR.A (octal transceiver, 20-pin) and SN74LV574ADGVR (octal flip-flop, 20-pin) are both Active/Production as of a September 2025 addendum. Meanwhile SN74AHC08DGVR.A (quad AND gate, 14-pin), SN74CBT3244DGVR.A (bus switch, 20-pin), and PCA9546ADGVR.A (I2C switch, 16-pin) are all marked NRND.

In other words: don’t treat “TVSOP” as a single lifecycle bucket. Some specific TVSOP-packaged parts are current and recommended; others from the same family are winding down; some from other vendors have been gone for over two decades. Check the specific part number, not the package name.

TVSOP vs. TSSOP vs. SSOP vs. LFBGA — A Real Head-to-Head

TI ran a direct comparison using the same 16-bit Widebus buffer function (SN74LVCH16244A) implemented in 48-pin SSOP, 48-pin TSSOP, 48-pin TVSOP, and a 96-pin LFBGA. This is the closest thing to a controlled experiment across these four package types, and it produced real numbers competitor pages don’t have:

Metric	SSOP 48-pin	TSSOP 48-pin	TVSOP 48-pin	LFBGA 96-ball
Board space per bit	10.69 mm²	6.65 mm²	4.14 mm²	2.32 mm²
Max pin capacitance	0.443 pF	0.410 pF	0.296 pF	0.145 pF
Max lead inductance	7.97 nH	3.99 nH	4.31 nH	2.866 nH
θJA, no airflow	93.5°C/W	89.1°C/W	92.9°C/W	40°C/W
θJA, 2.78 m/s airflow	57.1°C/W	69.4°C/W	71°C/W	35.7°C/W

Two findings worth flagging. TVSOP had the lowest maximum pin capacitance of the three dual-in-line packages and, per TI’s own conclusion, produced the best (lowest) ground-bounce and simultaneous-switching propagation-delay results of the Widebus dual-in-line options — a genuine electrical advantage, not just a space one. But TVSOP’s thermal picture is a real trade-off: it starts close to SSOP with no airflow (92.9 vs. 93.5°C/W) and improves less with forced-air cooling than SSOP does (71 vs. 57.1°C/W at 2.78 m/s) — the smaller package has less surface area to exploit moving air.

Worked calculation — junction temperature: Using the report’s own example power dissipation of ~0.5 W for a Widebus driver at TA = 25°C with no airflow, and the θJA values above: TJ = θJA × P + TA gives 71.75°C for SSOP, 69.55°C for TSSOP, 71.45°C for TVSOP, and 45°C for LFBGA. TVSOP and SSOP land within half a degree of each other here — TVSOP’s board-space win doesn’t come with a thermal win over SSOP at zero airflow.

Assembly: Pad Geometry, Stencils, and Placement Precision

At 0.40 mm pitch, TVSOP assembly is meaningfully less forgiving than TSSOP. TI’s own manufacturing evaluation and a separate AVEX Electronics production run both published concrete pad/stencil numbers, and they don’t fully agree with each other — worth knowing before you pick one:

• TI Custom Manufacturing Services: pad length 1.8 mm, pad width 0.28 mm, pad pitch 0.4 mm, ENTEK finish, 0.006 in. (0.15 mm) stencil for boards mixing PLCC and TVSOP, 0.005 in. (0.13 mm) for TVSOP-only boards.
• AVEX Electronics: pad length 1.57 mm, pad width 0.23 mm, pad pitch 0.40 mm, ENTEK or gold finish, 0.005 in. (0.13 mm) stencil, with 7-mil apertures outperforming 8-mil in their yield comparison.

The bigger yield driver isn’t pad geometry, though — it’s placement. TI’s data on widely spaced 0.40 mm-pitch devices (TVSOP has leads on two sides only, unlike a QFP) shows defect rates hold flat out to 8 inches from the PCB’s stencil-alignment center when leads are oriented parallel to the board’s image-stretch axis, then climb sharply beyond that: roughly 2x by 8 in., 4x by 9 in., 10x by 10 in., and 30x by 11 in. A 0.40 mm-pitch QFP (leads on all four sides) degrades far earlier and worse — normally-oriented QFPs show defects starting at just 4 inches from center and reaching 250x by 7 inches, though rotating the QFP 45° from the board’s expansion axis holds that off until roughly 9 inches. If you’re placing TVSOP devices near the edge of a large panel, lead orientation relative to the panel’s stretch axis is not optional.

Moisture Sensitivity

TVSOP packages are tested to JESD A112 for moisture sensitivity. Anything that doesn’t meet Level 1 gets dry-packed, with floor life scaling down from unlimited at Level 1 to as little as 6 hours at Level 6:

MSL Level	Floor life conditions	Duration
1	≤30°C at 90% RH	Unlimited
2	≤30°C at 60% RH	1 year
3	≤30°C at 60% RH	168 hours
4	≤30°C at 60% RH	72 hours
5	≤30°C at 60% RH	24 hours
6	≤30°C at 60% RH	6 hours

Check the specific device’s MSL rating and floor-life card before opening a dry-pack bag — this table shows the standard’s tiers, not a guarantee for any one part.

Real Parts in TVSOP

Historically, TVSOP was heavily used for wide (16- and 32-bit) TI logic bus buffers, transceivers, and translators — the SN74ALVCH16xxx, SN74ABT16xxx, and SN74LVCH16xxx families in 48/56-pin DGV, and the same families extending to 80/100-pin DBB. That’s a genuinely different application space than TSSOP-8 or TSSOP-64 — TVSOP’s niche was always wide parallel logic, not small analog ICs.

Currently active examples confirmed directly against TI’s own package option addenda include the SN74CB3T3245 bus switch (20-pin DGV), SN74AHC573 octal transceiver (20-pin DGV), SN74AHC138 3-to-8 decoder (16-pin DGV), and SN74LV574A octal flip-flop (20-pin DGV) — all still Active as of 2025–2026 addenda.

Selection Path

• You’re reviving or repairing a board with legacy IDT/FCT/FST logic in TVSOP → check the PDN first; many of those exact parts were discontinued in 2001–2002 with no direct replacement offered.
• You’re specifying a new TI logic function and TVSOP shows up as an option → check that specific orderable part number’s lifecycle status individually; don’t assume the whole package family shares one status.
• You need the absolute smallest board footprint for a wide parallel bus and can tolerate 0.40 mm-pitch assembly → TVSOP still beats TSSOP on space and, per TI’s own data, on simultaneous-switching noise.
• You need better thermal performance than SSOP/TSSOP/TVSOP all offer at similar levels, or you’re pin-limited well past 100 → LFBGA or a modern QFN/BGA option is the realistic modern path; TVSOP was effectively the last dual-in-line small-outline package before the industry moved to area-array packages for this level of miniaturization.

FAQ

What is a TVSOP package?

Thin Very Small Outline Package — a Texas Instruments surface-mount package family with a 0.40 mm lead pitch and 1.2 mm max height, registered under JEDEC MO-194, originally built to meet the PCMCIA card height limit.

Is the TVSOP package obsolete?

Not uniformly. IDT discontinued a batch of TVSOP logic parts in 2001–2002, but Texas Instruments still lists some TVSOP parts as Active in 2025–2026 package addenda, alongside others marked NRND. Check the specific part number.

How is TVSOP different from TSSOP?

TVSOP uses a finer 0.40 mm pitch versus TSSOP’s 0.5/0.65 mm, and is 24–38% smaller in area than the equivalent TSSOP part at the same pin count, per TI’s own comparison data. Both share a 1.2 mm max height.

What is the lead pitch of a TVSOP package?

0.40 mm across all eight pin-count variants (14 through 100 pins).

Can TVSOP be hand-soldered?

It’s not realistic. At 0.40 mm pitch, TI’s own manufacturing data shows even automated placement is highly sensitive to lead orientation and stencil precision — reflow with a properly specified stencil is the only practical path.

What replaced TVSOP in modern designs?

For most new designs needing this level of miniaturization, QFN handles lower pin counts and BGA (including TI’s own LFBGA) handles higher pin counts and denser I/O, generally with better thermal performance than any dual-in-line small-outline package offers.

What to Do Next

Don’t assume “TVSOP” means either “obsolete” or “available” — check the specific orderable part number’s lifecycle status on the manufacturer’s site before you commit a BOM line. If you’re specifying new, match the pin count to the correct JEDEC MO-194 variation and TI package code (DGV for 14–56 pins, DBB for 80–100), pull the pad geometry from a current manufacturer source rather than estimating it, and if the part is going near the edge of a large panel, orient the leads parallel to the board’s image-stretch axis to avoid the placement-defect climb TI’s own data documents.

Suggested internal links

• TSSOP-64 package dimensions, pinout, and footprint → package reference
• TSSOP-8 package dimensions, pinout, and footprint → package reference
• QFN vs BGA package selection for high pin-count logic → package selection guide
• How to read a JEDEC package outline drawing → package fundamentals

External sources referenced

Texas Instruments SCBA009E, “Thin Very Small-Outline Package (TVSOP)” application report (2001) · Texas Instruments SCYA007, “Comparison of Electrical and Thermal Parameters of Widebus SMD SSOP, TSSOP, TVSOP, and LFBGA Packages” (1999) · Renesas/IDT Product Discontinuance Notice PDN LOGIC-01-01 (2001) · Texas Instruments package option addenda for SN74CB3T3245, SN74AHC573, SN74LV574A, SN74AHC138, SN74AHC08, SN74CBT3244, and PCA9546A (2025–2026)